公开(公告)号：US4546455A

公开(公告)日：1985-10-08

申请号：US446669

申请日：1982-12-03

Applicant: Hiroshi Iwahashi ,  Kiyofumi Ochii

Inventor： Hiroshi Iwahashi ,  Kiyofumi Ochii

IPC: G11C29/00 ,  G11C11/40

CPC classification number: G11C29/785 ,  G11C29/83

Abstract: A programming circuit used with a semiconductor memory comprising normal as well as spare memory cells allows any of the normal memory cells to be replaced by a spare memory cell and includes a fuse and a MOSFET connected in series between first and second power supply terminals. A voltage signal at the junction between the fuse and the MOSFET is delivered to the gate of the MOSFET after being delayed after power is supplied.

Abstract translation: 与包括正常以及备用存储单元的半导体存储器一起使用的编程电路允许任何正常存储器单元被备用存储单元替换，并且包括串联连接在第一和第二电源端子之间的保险丝和MOSFET。 保险丝和MOSFET之间的连接处的电压信号在供电后被延迟后传送到MOSFET的栅极。

公开(公告)号：US4477884A

公开(公告)日：1984-10-16

申请号：US310822

申请日：1981-10-13

Applicant: Hiroshi Iwahashi ,  Masamichi Asano

Inventor： Hiroshi Iwahashi ,  Masamichi Asano

IPC: G11C7/22 ,  G11C8/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C29/34 ,  G11C7/00

CPC classification number: G11C29/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/32 ,  G11C7/22 ,  G11C8/12

Abstract: A semiconductor memory comprising a memory array having a plurality of memory cells, such as floating gate type MOS transistors, arranged in a matrix form with column lines and row lines, and a plurality of bit outputs. The plurality of column lines are associated with each bit output. A circuit is provided which applies a program voltage to a plurality of column lines corresponding to each bit output in response to address signals or control signals. A plurality of memory cells corresponding to each bit output are programmed simultaneously by the circuit.

Abstract translation: 一种半导体存储器，包括具有多个存储单元的存储器阵列，诸如浮栅型MOS晶体管，其以列线和行线排列成矩阵形式，以及多个位输出。 多个列线与每个位输出相关联。 提供了一种电路，其响应于地址信号或控制信号将编程电压施加到对应于每个位输出的多个列线。 对应于每个位输出的多个存储单元由电路同时编程。

公开(公告)号：US4467457A

公开(公告)日：1984-08-21

申请号：US329059

申请日：1981-12-09

Applicant: Hiroshi Iwahashi ,  Masamichi Asano

Inventor： Hiroshi Iwahashi ,  Masamichi Asano

IPC: G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  H01L29/788 ,  G11C11/21

CPC classification number: H01L29/7881 ,  G11C16/28 ,  G11C16/34 ,  G11C29/50 ,  G11C16/04

Abstract: Disclosed is a nonvolatile semiconductor memory device in which the difference in level between a reference signal and the output signal of a memory array formed of floating gate MOS FETs is decided by means of a differential sense amplifier, and the result of the decision provides memory data. The reference signal is produced by a gate signal generator which produces a gate signal at a fixed voltage level at the time of testing and a gate signal at a voltage level obtained by dividing the supply voltage at the time of normal reading, and a reference signal generator which produces a reference signal at a level corresponding to the conductive resistance of a floating gate MOS FET with the same configuration of each memory cell whose control gate is supplied with the gate signal.

Abstract translation: 公开了一种非易失性半导体存储器件，其中通过差分读出放大器确定参考信号和由浮置栅极MOS FET形成的存储器阵列的输出信号之间的电平差，并且判定结果提供存储器数据 。 参考信号由门信号发生器产生，该门信号发生器在测试时产生固定电压电平的栅极信号，并且通过在正常读取时除以电源电压获得的电压电平的栅极信号和参考信号 发生器，其以与控制栅极被提供有栅极信号的每个存储单元相同配置的浮动栅极MOS FET的导电电阻的相应电平产生参考信号。

公开(公告)号：US4453174A

公开(公告)日：1984-06-05

申请号：US152292

申请日：1980-05-22

Applicant: Yuichi Kawasaki ,  Sumio Tanaka ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Shinichi Maekawa ,  Masazi Mito

Inventor： Yuichi Kawasaki ,  Sumio Tanaka ,  Hiroshi Iwahashi ,  Masamichi Asano ,  Shinichi Maekawa ,  Masazi Mito

IPC: H01L21/76 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L29/02

CPC classification number: G11C16/0416 ,  H01L27/088 ,  H01L27/105

Abstract: Disclosed is a metal oxide semiconductor integrated circuit device having an array of electrically rewritable, insulated gate type non-volatile semiconductor memory cells formed on a semiconductor substrate, read/write mode setting circuit and address designating circuits arranged corresponding to the memory cell array, those circuits being fabricated on the substrate, and a field insulating layer formed on the substrate. A cut portion is formed in the field insulating layer to surround the memory cell array.

Abstract translation: 公开了一种金属氧化物半导体集成电路器件，其具有形成在半导体衬底上的电可重写绝缘栅型非易失性半导体存储单元阵列，读/写模式设置电路和对应于存储单元阵列布置的地址指定电路 在衬底上制造的电路和形成在衬底上的场绝缘层。 在场绝缘层中形成切割部分以包围存储单元阵列。

公开(公告)号：US4425632A

公开(公告)日：1984-01-10

申请号：US180991

申请日：1980-08-25

Applicant: Hiroshi Iwahashi ,  Masamichi Asano

Inventor： Hiroshi Iwahashi ,  Masamichi Asano

IPC: H01L27/112 ,  G11C16/04 ,  G11C16/06 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC classification number: G11C16/0416

Abstract: There is provided a nonvolatile semiconductor memory device which comprises memory cells arranged in the form of a matrix and formed of MOS FET's each having a floating gate, a plurality of word lines each coupled to memory cells on the same row, and a plurality of data lines each coupled to memory cells on the same column. In this semiconductor memory device, the sources of the MOS FET's forming the memory cells are coupled to a resistor.

Abstract translation: 提供了一种非易失性半导体存储器件，其包括以矩阵形式布置并由各自具有浮置栅极的MOS FET形成的存储器单元，每个耦合到同一行上的存储器单元的多个字线和多个数据 每条线都耦合到同一列上的存储器单元。 在该半导体存储器件中，形成存储单元的MOS FET的源极耦合到电阻器。

公开(公告)号：US20050007821A1

公开(公告)日：2005-01-13

申请号：US10897084

申请日：2004-07-21

Applicant: Hiroshi Iwahashi

Inventor： Hiroshi Iwahashi

IPC: G11C16/04 ,  G11C16/12 ,  G11C8/00

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the date latch circuits can be formed at any positions remote from the memory cell array.

Abstract translation: 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任一个存储在存储单元组或块的存储单元中，负阈值电压被分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，日期锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06738293B1

公开(公告)日：2004-05-18

申请号：US10413826

申请日：2003-04-15

Applicant: Hiroshi Iwahashi

Inventor： Hiroshi Iwahashi

IPC: G11C1604

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/26

Abstract: In a non-volatile semiconductor memory, a large current can be flowed through the memory cell during reading. The number of the column lines can be reduced. The electron injection to the floating gates of the respective memory cells is averaged to reduce the dispersion of the threshold voltages thereof. The electron emission from the floating gates of the respective memory cells is also averaged to reduce the dispersion of the threshold voltages thereof. An increase in chip size due to latch circuits can be prevented. By noting that either of a plurality of “0” or “1” of the binary data are stored such in the memory cells of the memory cell bundle or block, a negative threshold voltage is allocated to the memory cells for storing the more bit side data of the binary data. A single column line is used in common for the two adjacent memory blocks. To inject electrons to the floating gates of the memory cells, voltage is increased gradually and stopped when electrons have been injected up to a predetermined injection rate. Electrons are once emitted from the floating gates, and thereafter the electrons are injected again to store one of a binary data. Further, the data latch circuits can be formed at any positions remote from the memory cell array.

Abstract translation: 在非易失性半导体存储器中，在读取期间可以通过存储单元流过大电流。 可以减少列线的数量。 对各个存储单元的浮置栅极的电子注入被平均以减小其阈值电压的偏差。 来自相应存储单元的浮置栅极的电子发射也被平均以减小其阈值电压的偏差。 可以防止由于锁存电路引起的芯片尺寸的增加。 通过注意到二进制数据的多个“0”或“1”中的任一个存储在存储单元组或块的存储单元中，负阈值电压被分配给用于存储更多位侧的存储单元 二进制数据的数据。 对于两个相邻的存储器块，共同使用单列线。 为了将电子注入存储单元的浮动栅极，电压逐渐增加并且当电子注入到预定的注入速率时停止。 电子一次从浮动栅极发射，此后再次注入电子以存储二进制数据之一。 此外，数据锁存电路可以形成在远离存储单元阵列的任何位置处。

公开(公告)号：US06545913B2

公开(公告)日：2003-04-08

申请号：US10052742

申请日：2002-01-23

Applicant: Hiroshi Iwahashi

Inventor： Hiroshi Iwahashi

IPC: G11C1606

CPC classification number: G11C16/12 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A row line selection circuit comprises first and second decoding sections and NMOS transistors. The first decoding section receives a first address signal and generates first selection signals. The second decoding section receives a second address signal and generates second selection signals. The NMOS transistors each of which has a gate for receiving one of the first selection signals, one end of a current path of each of the NMOS transistors being connected to receive the one of the second selection signals. The NMOS transistors classified into groups, each group including a predetermined number of the transistors which are prepared in correspondence with row lines lying adjacent to each other. One of the first selection signals is supplied to the predetermined number of NMOS transistors in one of the groups, and one of the second selection signals is supplied to one of the predetermined number of NMOS transistors in each group.

Abstract translation: 行线选择电路包括第一和第二解码部分和NMOS晶体管。 第一解码部分接收第一地址信号并产生第一选择信号。 第二解码部分接收第二地址信号并产生第二选择信号。 每个NMOS晶体管具有用于接收第一选择信号之一的NMOS晶体管，每个NMOS晶体管的电流路径的一端被连接以接收第二选择信号中的一个。 分成组的NMOS晶体管，每组包括与彼此相邻的行线对应地准备的预定数量的晶体管。 第一选择信号之一被提供给组中的一个中的预定数量的NMOS晶体管，并且第二选择信号中的一个被提供给每组中的预定数量的NMOS晶体管中的一个。

公开(公告)号：US06452853B2

公开(公告)日：2002-09-17

申请号：US09901055

申请日：2001-07-10

Applicant: Hiroshi Iwahashi

Inventor： Hiroshi Iwahashi

IPC: G11C700

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/08 ,  G11C2211/5642

Abstract: A nonvolatile semiconductor memory includes a memory cell string containing a selection transistor and at least one cell transistor which is connected to the selection transistor and has a floating gate. Cell transistors are arranged in a memory cell array. The transistors each have a charge accumulation layer. A potential supply circuit supplies a potential different from a ground potential to gates of the cell transistor at least read operation and when the memory cell array is unselected.

Abstract translation: 非易失性半导体存储器包括存储单元串，其包含选择晶体管和至少一个单元晶体管，其连接到选择晶体管并具有浮置栅极。 单元晶体管布置在存储单元阵列中。 晶体管各自具有电荷累积层。 电位供应电路至少读取操作和当未选择存储单元阵列时，将与地电势不同的电位提供给单元晶体管的栅极。

公开(公告)号：US06269021B1

公开(公告)日：2001-07-31

申请号：US09261458

申请日：1999-02-26

Applicant: Hiroshi Iwahashi

Inventor： Hiroshi Iwahashi

IPC: G11C1604

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30

Abstract: The current paths of a plurality of floating gate type MOSFETs are series-connected to form a series circuit. The series circuit is connected at one end to receive a reference voltage, and is connected to data programming and readout circuit. In the data programming mode, electrons are discharged from the floating gate to the drain of the MOSFET or holes are injected into the drain into the floating gate. The data readout operation is effected by checking whether current flows from the other end to the one end of the series circuit or not.

Abstract translation: 多个浮栅型MOSFET的电流路径串联连接形成串联电路。 该串联电路一端连接以接收参考电压，并连接到数据编程和读出电路。 在数据编程模式下，电子从浮置栅极放电到MOSFET的漏极，或者将漏极注入到浮动栅极中。 数据读出操作通过检查电流是否从串联电路的另一端流向一端来实现。