公开(公告)号：US20240243093A1

公开(公告)日：2024-07-18

申请号：US18519652

申请日：2023-11-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Koji OSAKI ,  Yuichiro HINATA

IPC: H01L23/00

CPC classification number: H01L24/40 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/4007 ,  H01L2224/40229 ,  H01L2224/73263 ,  H01L2924/13055

Abstract: A semiconductor module includes a semiconductor chip arranged on a mounting board, and a wiring member electrically connected to the semiconductor chip. The wiring member includes a body portion elongated in the direction of a Y-axis, and one or more ridges protruding from a surface of a flat plate-shaped portion of the body portion and extending along the Y-axis.

公开(公告)号：US12040361B2

公开(公告)日：2024-07-16

申请号：US17533855

申请日：2021-11-23

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Keiji Okumura

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/1608

Abstract: A semiconductor device includes n-type drift layer, n-type first current spreading layer on top surface of the drift layer, p-type base region on top surface of the first current spreading layer, p-type gate-bottom protection region inside the first current spreading layer, p-type base-bottom embedded region separated from the gate-bottom protection region and in contact with bottom surface of the base region, n-type second current spreading layer having side surface opposed to the gate-bottom protection region and in contact with side surface of the base-bottom embedded region, and insulated gate electrode structure inside trench penetrating the base region to reach the gate-bottom protection region. The impurity concentration ratio of the gate-bottom protection region to the first current spreading layer is greater than the impurity concentration ratio of the base-bottom embedded region to the second current spreading layer.

公开(公告)号：US20240235417A9

公开(公告)日：2024-07-11

申请号：US18453925

申请日：2023-08-22

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hironobu SHIROYAMA

IPC: H02M7/219 ,  H02M1/42

CPC classification number: H02M7/219 ,  H02M1/4208

Abstract: A control circuit for a circuit that has a rectifier circuit including first to fourth diodes, and first to fourth switches respectively connected in parallel with the first to fourth diodes, for rectifying an AC voltage; and a capacitor receiving the rectified AC voltage. The control circuit controls the first to fourth switches, and includes: a determination unit determining an off-period in which, when the AC voltage is applied, the first to fourth diodes turn off, the off-period including a first period and a second period, in which the first and fourth diodes, and the second and third diodes, respectively turn off; and a control unit turning on the first and fourth switches in the first period, when the second and third diodes are off, and turning on the second and third switches in the second period, when the first and fourth diodes are off.

公开(公告)号：US20240234554A1

公开(公告)日：2024-07-11

申请号：US18515275

申请日：2023-11-21

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Naoki MITAMURA

IPC: H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L29/7397 ,  H01L27/0727 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/861

Abstract: Provided is a semiconductor device including a transistor portion and a diode portion, where the semiconductor device including: a plurality of trench portions provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; an anode region of a second conductivity type provided above the drift region in the diode portion; a low concentration region provided above the anode region and having a doping concentration an absolute value of which is lower than that of the anode region; and a high concentration region of the second conductivity type provided above the anode region and having a doping concentration higher than that of the anode region.

公开(公告)号：US20240234496A1

公开(公告)日：2024-07-11

申请号：US18399996

申请日：2023-12-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Kensuke TAKENAKA ,  Shinsuke HARADA

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: A method of manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide semiconductor substrate of a first conductivity type; forming a first semiconductor layer of a first conductivity type at a surface of the silicon carbide semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the silicon carbide semiconductor substrate; implanting ions of an inert element into a region of a surface layer of the first semiconductor layer, thereby, inducing ion implantation damage to a crystal structure of the region in which a long tail occurs, the surface layer being at the first surface of the first semiconductor layer; and implanting a dopant of a second conductivity type into the surface layer of the first semiconductor layer where the crystal structure is damaged, thereby, forming column regions of the second conductivity type.

公开(公告)号：US20240234266A1

公开(公告)日：2024-07-11

申请号：US18522852

申请日：2023-11-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L23/495

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49562 ,  H02P27/06

Abstract: A semiconductor device 100A includes drive chips 21[k], a control chip 41A including a plurality of terminals H including a voltage terminal Hc and power supply terminals Hb[k] and configured to control each of the drive chips 21[k], using a corresponding one of power supply voltages Vb[k] supplied to a corresponding one of the power supply terminals Hb[k], a die pad 63 for supplying control voltage Vcc to the voltage terminal Hc, wires Qb[k] each connected to a corresponding one of the power supply terminals Hb[k] and for supplying a corresponding one of the power supply voltages Vb[k] to a corresponding one of the power supply terminals Hb[k], and a semiconductor chip 30A used for bootstrap operation to generate the power supply voltages Vb[k] and including diodes the number of which is the same as the number of the power supply voltages Vb[k].

公开(公告)号：US20240234261A1

公开(公告)日：2024-07-11

申请号：US18523157

申请日：2023-11-29

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/4952 ,  H01L23/4951 ,  H01L23/49575 ,  H01L24/33 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/3301 ,  H01L2224/33515 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/01029 ,  H01L2924/13055 ,  H01L2924/1427

Abstract: A semiconductor device includes a plurality of power semiconductor elements and a control chip including a plurality of terminals including a first terminal and a plurality of second terminals and configured to control the plurality of power semiconductor elements, using power supply voltage supplied to the plurality of second terminals. The semiconductor device also includes a first conductor for supplying a predetermined control voltage to the first terminal, a plurality of first wirings individually connected to the plurality of second terminals and for supplying the power supply voltage to the plurality of the second terminals, a die pad on which the control chip is arranged, and a semiconductor chip including a diode used for bootstrap operation to generate the power supply voltage. The semiconductor chip is fixed to the die pad by an insulating material. The die pad is connected to a terminal to which a reference voltage is supplied.

公开(公告)号：US12033984B2

公开(公告)日：2024-07-09

申请号：US18316783

申请日：2023-05-12

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Mitsuhiro Kakefu ,  Hiroaki Ichikawa

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L25/072 ,  H01L23/49844 ,  H01L24/48 ,  H01L29/7393 ,  H01L29/861 ,  H01L2224/48225

Abstract: A semiconductor device including a semiconductor unit that has a first arm part, which includes: first and second semiconductor chips having first and second control electrodes on their front surfaces, a first circuit pattern where the first and second semiconductor chips are disposed, a second circuit pattern to which the first and second control electrodes are connected, and a first control wire electrically connecting the first and second control electrodes and the second circuit pattern sequentially in a direction; and a second arm part, which includes third and fourth semiconductor chips having third and fourth control electrodes on their front surfaces, a third circuit pattern where the third and fourth semiconductor chips are disposed, a fourth circuit pattern to which the third and fourth control electrodes are connected, and a second control wire electrically connecting the third and fourth control electrodes and the fourth circuit pattern sequentially in the direction.

公开(公告)号：US20240213311A1

公开(公告)日：2024-06-27

申请号：US18497333

申请日：2023-10-30

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Syunki NARITA ,  Shinsuke HARADA

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/7813

Abstract: In an active region and an edge termination region, a drift layer is constituted by a same SJ structure with a parallel pn layer. In the edge termination region, a p+-type extension portion between the active region and a JTE structure fixes the JTE structure to the potential of a source electrode. The p+-type extension portion is between and in contact with a p-type base extension portion and the parallel pn layer. The p+-type extension portion is an extension of upper portions of p+-type regions provided in the active region to mitigate electric field near bottoms of gate trenches. Between the p-type base extension portion and the parallel pn layer is free of the lower portions of the p+-type regions. Thus, a length in the depth direction of the p-type column regions of the edge termination region is longer than that of the p-type column regions of the active region.

公开(公告)号：US20240213307A1

公开(公告)日：2024-06-27

申请号：US18427607

申请日：2024-01-30

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Tomohiro MORIYA ,  Akimasa KINOSHITA

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/04 ,  H01L29/16 ,  H01L29/423

CPC classification number: H01L29/06 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/4236

Abstract: A p-type impurity concentration profile in a depth direction of a p-type base region is adjusted by two or more stages of ion implantation to the p-type base region. The two or more stages of ion implantation are each set to have a mutually different acceleration voltage and a dose amount that is lower the higher is the acceleration voltage. The p-type impurity concentration profile is asymmetrical about a depth position of a highest impurity concentration and the impurity concentration decreases from this depth position in a direction to n+-type source regions and in a direction to an n+-type drain region. In the p-type impurity concentration profile, the impurity concentration decreases, forming a step at one or more different depth positions closer to the n+-type drain region than is the depth position of the highest impurity.