公开(公告)号：US20230187437A1

公开(公告)日：2023-06-15

申请号：US17975207

申请日：2022-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L27/02

CPC classification number: H01L27/0296 ,  H01L27/0255 ,  H01L27/0288

Abstract: A semiconductor device includes: a semiconductor base body; a first region of a first conductivity type selectively provided in an upper part of the semiconductor base body; a second region of a second conductivity type provided in contact with the first region in the upper part of the semiconductor base body; a third region of the second conductivity type provided away from the second region in the upper part of the semiconductor base body; a fourth region of the second conductivity type provided between the second region and the third region in the upper part of the semiconductor base body; a first isolation region provided between the second region and the fourth region; and a second isolation region provided between the third region and the fourth region.

公开(公告)号：US20160056282A1

公开(公告)日：2016-02-25

申请号：US14781244

申请日：2014-06-06

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7818 ,  H01L21/761 ,  H01L21/764 ,  H01L27/0629 ,  H01L27/0727 ,  H01L27/1207 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/7393 ,  H01L29/78 ,  H01L29/8611 ,  H03K17/002

Abstract: In a semiconductor device including a bootstrap diode and a high voltage electric field transistor on a p-type semiconductor substrate, a cavity is formed in an n−-type buried layer of the semiconductor substrate to use the buried layer beneath the cavity as a drain drift region of the high voltage n-channel MOSFET, whereby a leakage current by holes that flows to the semiconductor substrate side in forward biasing of the bootstrap diode can be suppressed, and charging current for a bootstrap capacitor C1 can be increased, as well as increase in chip area can be suppressed.

Abstract translation: 在包括p型半导体衬底上的自举二极管和高电压电场晶体管的半导体器件中，在半导体衬底的n型掩埋层中形成空穴，以使用腔下面的掩埋层作为漏极 漂移区域，从而可以抑制在自举二极管的正向偏置中流向半导体衬底侧的空穴的漏电流，并且可以增加自举电容器C1的充电电流，以及 可以抑制芯片面积的增加。

公开(公告)号：US20160056148A1

公开(公告)日：2016-02-25

申请号：US14792027

申请日：2015-07-06

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi KANNO ,  Hitoshi SUMIDA ,  Masaharu YAMAJI

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/7395

Abstract: A semiconductor device is provided with a first well region of a first conduction type having a first voltage (voltage VB) applied thereto, a second well region of a second conduction type formed in the surface layer section of the first well region and having a second voltage (voltage VS) different from the first voltage applied thereto, and a charge extracting region of the first conduction type formed in the surface layer section of the second well region and having the first voltage applied thereto. This inhibits the operation of a parasitic bipolar transistor.

Abstract translation: 半导体器件设置有具有施加到其上的第一电压（电压VB）的第一导电类型的第一阱区域，形成在第一阱区域的表层部分中的第二导电类型的第二阱区域，并且具有第二阱区域 电压（电压VS）与施加到其上的第一电压不同的第一导电类型的电荷提取区域，以及形成在第二阱区的表层部分中并具有第一电压的电荷提取区域。 这抑制了寄生双极晶体管的工作。

公开(公告)号：US20150236013A1

公开(公告)日：2015-08-20

申请号：US14622819

申请日：2015-02-13

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L29/0634 ,  H01L21/761 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H03K17/18 ,  H03K19/018571 ,  H03K2217/0063

Abstract: A high voltage integrated circuit device suppresses the quantity of holes that are implanted due to a negative voltage surge, thus preventing malfunction and destruction of a high side circuit. A p−-type aperture portion has a gap portion in an n-type well region that is a voltage resistant region, penetrating the n-type well region to reach a p-type substrate, so as to enclose an n-type well region that is a high potential region.

Abstract translation: 高电压集成电路器件抑制由于负电压浪涌而被注入的空穴的量，从而防止高侧电路的故障和破坏。 p型开口部在作为耐电压区域的n型阱区域中具有贯通n型阱区域到达p型衬底的间隙部分，以包围n型阱区域 这是一个高潜力地区。

公开(公告)号：US20140191281A1

公开(公告)日：2014-07-10

申请号：US14204909

申请日：2014-03-11

Applicant: FUJI ELECTRIC CO., LTD

Inventor： Masaharu YAMAJI

IPC: H01L29/739 ,  H01L29/78

CPC classification number: H01L21/761 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7832

Abstract: An n well region and an n−region surrounding the n well region are provided in the surface layer of a p−silicon substrate. The n−region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p− opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p−opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.

Abstract translation: n阱区和围绕n阱区的n区设置在p-硅衬底的表面层中。 n区域包括设置高压MOSFET的击穿电压区域。 n阱区域包括布置有逻辑电路的逻辑电路区域。 在每个高压MOSFET的漏极区域和逻辑电路区域之间设置p-开口部分。 在第二拾取区域和漏极区域之间设置用作负载电阻的n个缓冲区域。 p开口部设置在n个缓冲区域和逻辑电路区域之间。 通过这样做，可以实现芯片面积的减小，并且提供具有高开关响应速度的电平移位电路的高电压半导体器件。

公开(公告)号：US20230187438A1

公开(公告)日：2023-06-15

申请号：US17974894

申请日：2022-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/808

CPC classification number: H01L27/0629 ,  H01L28/20 ,  H01L29/808

Abstract: A semiconductor device includes: an n+-type drain region deposited at an upper part of a p-type semiconductor base body; an n-type drift region deposited to be in contact with the n+-type drain region; an n+-type source region opposed to the n+-type drain region with the n-type drift region interposed; a p-type gate region deposited to be in contact with the n-type drift region; an interlayer insulating film covering the n-type drift region; a resistive element having a spiral-like planar shape provided inside the interlayer insulating film; a drain electrode wire connected to the n+-type drain region and one end of the resistive element; a source electrode wire connected to the n+-type source region; a gate electrode wire connected to the p-type gate region; and a potential-dividing terminal wire connected to the resistive element, wherein a gap between the source electrode wire and an outermost circumference of the resistive element is constant.

公开(公告)号：US20220190107A1

公开(公告)日：2022-06-16

申请号：US17511688

申请日：2021-10-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L29/06 ,  H01L27/092 ,  H01L27/06 ,  H01L29/739 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes: a well region of a second conductivity-type deposited on a surface layer of a semiconductor layer of a first conductivity-type; a breakdown voltage region of the second conductivity-type arranged to surround the well region and having a lower impurity concentration than the well region; a base region of the first conductivity-type arranged to surround the breakdown voltage region; a carrier supply region of the second conductivity-type arranged on a surface layer of the base region and serving as a level shifter; and a carrier reception region of the level shifter, wherein the carrier reception region is formed of a first universal contact region including a region of the first conductivity-type and a region of the second conductivity-type arranged in contact with each other.

公开(公告)号：US20210013203A1

公开(公告)日：2021-01-14

申请号：US17034856

申请日：2020-09-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi KANNO ,  Masaharu YAMAJI ,  Hitoshi SUMIDA

IPC: H01L27/092 ,  H01L23/00 ,  H01L29/06 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.

公开(公告)号：US20200161418A1

公开(公告)日：2020-05-21

申请号：US16580661

申请日：2019-09-24

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L21/266

Abstract: A semiconductor integrated circuit includes: a semiconductor base body of a first conductivity type; a first well region of a second conductivity type, deposited at an upper portion of the semiconductor base body, to which a first potential is applied; a second well region of the first conductivity type, deposited at an upper portion of the first well region, to which a second potential lower than the first potential is applied; a main electrode region to which the second potential is applied, the main electrode region being deposited at the upper portion of the first well region and away from the second well region; a first buried layer of the second conductivity type buried locally under the second well region; and a second buried layer of the second conductivity type buried locally under the main electrode region and away from the first buried layer.

公开(公告)号：US20200044652A1

公开(公告)日：2020-02-06

申请号：US16528921

申请日：2019-08-01

Applicant: Fuji Electric Co., Ltd.

Inventor： Masaharu YAMAJI

IPC: H03K17/693

Abstract: In a level shifter circuit that transmits a set signal and a reset signal input to input terminals of a high-side latch circuit, the source sides of high voltage transistors are connected to current negative feedback resistors, and transistors are connected in parallel to the current negative feedback resistors. Further included is a high-side voltage detection circuit that detects whether the voltage of a high-side power supply terminal is a high voltage. When a high voltage is detected, the transistors are turned OFF to make the drain currents that flow smaller, thereby making it possible to improve the trade-off between heat generation and propagation delay characteristics in the high voltage transistors.