公开(公告)号：US20200044011A1

公开(公告)日：2020-02-06

申请号：US16455128

申请日：2019-06-27

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaru SAITO ,  Masaharu YAMAJI ,  Osamu SASAKI ,  Hitoshi SUMIDA

IPC: H01L49/02

Abstract: Provided is a resistance element, including: a semiconductor substrate; a first insulating film stacked on the semiconductor substrate; a resistance layer selectively stacked on the first insulating film; a first auxiliary film separated from the resistance layer; a second auxiliary film separated from the resistance layer in a direction different from that of the first auxiliary film; a second insulating film stacked on the first insulating film to cover the resistance layer, and the first auxiliary film and the second auxiliary film; a first electrode connected to the resistance layer and stacked on the second insulating film disposed on an upper side of the first auxiliary film; and a second electrode connected to the resistance layer by being separated from the first electrode and stacked on the second insulating film on the upper side of the second auxiliary film.

公开(公告)号：US20140145763A1

公开(公告)日：2014-05-29

申请号：US14170089

申请日：2014-01-31

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Akihiro JONISHI ,  Hitoshi SUMIDA

IPC: H03K17/081

CPC classification number: H03K17/08104 ,  H03K17/08142 ,  H03K17/163

Abstract: A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET.

Abstract translation: 一种用于驱动绝缘栅极开关元件的栅极驱动电路，包括：栅极充电电路，被配置为对绝缘栅极开关元件的栅极电容进行充电，栅极放电电路与栅极充电电路串联连接， 的栅极电容。 栅极充电电路包括第一p沟道金属氧化物半导体场效应晶体管（MOSFET）和与第一p沟道MOSFET的漏极串联连接的第一混合常闭增强型MOSFET插入（NOEMI）电路。 栅极放电电路包括与第一n沟道MOSFET的漏极串联连接的第一n沟道MOSFET和第二混合NOEMI电路。

公开(公告)号：US20130321094A1

公开(公告)日：2013-12-05

申请号：US13894624

申请日：2013-05-15

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hitoshi SUMIDA ,  Yoshiaki TOYODA ,  Masashi AKAHANE

IPC: H01P1/36 ,  H01L21/768

CPC classification number: H01P1/36 ,  H01F2019/085 ,  H01L21/76879 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/13022 ,  H01L2224/16238 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/13091 ,  H01L2224/13099 ,  H01L2924/00

Abstract: In certain aspects of the invention, an isolator is configured by a reception circuit, a transmission circuit, and a transformer. In some aspects, the transmission circuit is disposed in an anterior surface of a semiconductor substrate. The transformer is disposed in a posterior surface of the semiconductor substrate and transmits in an electrically isolated state to the reception circuit, a signal input from the transmission circuit. The transformer is configured by a primary coil and a secondary coil. The primary coil can be configured by a metal film embedded in an oxide film inside a coil trench. The secondary coil can be disposed inside an insulating film covering the primary coil so as to oppose the primary coil and is insulated from the primary coil by the insulating film.

Abstract translation: 在本发明的某些方面，隔离器由接收电路，发送电路和变压器构成。 在一些方面，传输电路设置在半导体衬底的前表面中。 变压器设置在半导体衬底的后表面中，并且以电隔离状态向接收电路发送从发送电路输入的信号。 变压器由初级线圈和次级线圈构成。 初级线圈可以由嵌入在线圈沟槽内的氧化物膜中的金属膜构成。 次级线圈可以布置在覆盖初级线圈的绝缘膜内，以与初级线圈相对，并且通过绝缘膜与初级线圈绝缘。

公开(公告)号：US20210013203A1

公开(公告)日：2021-01-14

申请号：US17034856

申请日：2020-09-28

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi KANNO ,  Masaharu YAMAJI ,  Hitoshi SUMIDA

IPC: H01L27/092 ,  H01L23/00 ,  H01L29/06 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor integrated circuit includes a first ion implantation process implanting impurity ions of a second conductivity type into a bottom surface of a semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a first current suppression layer, and a second ion implantation process implanting impurity ions of a first conductivity type into the bottom surface of the semiconductor substrate by adjusting an acceleration voltage and a projection range for forming a second current suppression layer. The semiconductor integrated circuit includes a first well region of the first conductivity type and a second well region of the second conductivity type provided in an upper portion of the first well region. The first current suppression layer is separated from the first well region and the second current suppression layer is provided under the first current suppression layer.

公开(公告)号：US20150200309A1

公开(公告)日：2015-07-16

申请号：US14560516

申请日：2014-12-04

Applicant: Fuji Electric Co., Ltd.

Inventor： Taichi KARINO ,  Hitoshi SUMIDA

IPC: H01L29/808

CPC classification number: H01L29/808 ,  H01L27/0248 ,  H01L27/0738 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/402 ,  H02M1/36 ,  H02M2001/0006

Abstract: In a high voltage JFET, a p-floating region is provided in the surface layer of an n-drift region, thereby increasing the resistance R of the n-drift region and minimizing the voltage divided at a pn junction. This makes it possible to improve ESD capacity without increasing device size and without making the cutoff current smaller.

Abstract translation: 在高电压JFET中，在n漂移区域的表面层中设置p浮动区域，从而增加n漂移区域的电阻R并使在pn结处分压的电压最小化。 这使得可以在不增加器件尺寸并且不使截止电流更小的情况下提高ESD容量。

公开(公告)号：US20220013466A1

公开(公告)日：2022-01-13

申请号：US17483181

申请日：2021-09-23

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Masaharu YAMAJI ,  Taichi KARINO ,  Hitoshi SUMIDA ,  Hideaki ITOH

IPC: H01L23/532 ,  H01L21/768 ,  H03K17/567

Abstract: A semiconductor device includes: a wiring layer; a titanium nitride layer deposited on the wiring layer; a titanium oxynitride layer deposited on the titanium nitride layer; a titanium oxide layer deposited on the titanium oxynitride layer; and a surface passivation film deposited on the titanium oxide layer, wherein an opening penetrating the titanium nitride layer, the titanium oxynitride layer, the titanium oxide layer, and the surface passivation film is provided to expose a part of the wiring layer so as to serve as a pad.

公开(公告)号：US20180372791A1

公开(公告)日：2018-12-27

申请号：US15959786

申请日：2018-04-23

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Takahiro MORI ,  Hitoshi SUMIDA ,  Masahiro SASAKI ,  Akira NAKAMORI ,  Masaru SAITO ,  Wataru TOMITA ,  Osamu SASAKI

IPC: G01R31/26 ,  H03K17/687 ,  G05F1/59 ,  G01R31/28

CPC classification number: G01R31/2621 ,  G01R31/2884 ,  G05F1/59 ,  H03K17/6871

Abstract: To provide a semiconductor integrated device capable of a gate screening test with no need for any additional circuit and without adding any gate screening terminal. The semiconductor integrated device includes a gate drive unit configured to drive the gate of a voltage controlled semiconductor element and a regulator configured to supply a gate drive voltage to the gate drive unit. The regulator includes an external connection terminal capable of receiving a gate screening voltage for the voltage controlled semiconductor element in a gate screening test.

公开(公告)号：US20180331102A1

公开(公告)日：2018-11-15

申请号：US16043889

申请日：2018-07-24

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi KANNO ,  Masaharu YAMAJI ,  Hitoshi SUMIDA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H02M1/08

Abstract: A semiconductor integrated circuit includes: a first well region of a first conductivity type; a second well region of a second conductivity type provided in an upper portion of the first well region; a first current suppression layer of a second conductivity type being provided to be separated from the first well region in a lower portion of a base-body of the second conductivity type directly under the first well region and having an impurity concentration higher than that of the base-body; and a second current suppression layer of the first conductivity type provided under the first current suppression layer so as to be exposed from a bottom surface of the base-body.

公开(公告)号：US20170133401A1

公开(公告)日：2017-05-11

申请号：US15415380

申请日：2017-01-25

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi KANNO ,  Hitoshi SUMIDA ,  Masaharu YAMAJI

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/84 ,  H01L23/00 ,  H01L23/498 ,  H03K17/687 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/76 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/49838 ,  H01L24/32 ,  H01L27/04 ,  H01L27/08 ,  H01L27/092 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/1095 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1426 ,  H03K17/687 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a semiconductor layer of a first conductivity type which is stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the supp ort substrate, a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer, a second well region of the first conductivity type buried in an upper part of the first well region, and an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer.

公开(公告)号：US20160020685A1

公开(公告)日：2016-01-21

申请号：US14734665

申请日：2015-06-09

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Hiroshi KANNO ,  Hitoshi SUMIDA

IPC: H02M1/08 ,  H02M7/537

CPC classification number: H02M1/08 ,  H02M7/538 ,  H03K17/04123

Abstract: A semiconductor device that has a level shift circuit, an anterior stage circuit, and a posterior stage circuit. The level shift circuit transmits an input signal from a primary potential system to a secondary potential system different from the primary potential system. The anterior stage circuit including a first transistor receives a gate driving signal delivered by the level shift circuit. The posterior stage circuit including a second transistor with the same channel type as that of the first transistor drives a switching element according to the output signal from the first transistor. The threshold voltage of the first transistor is set at a lower value than the threshold voltage of the second transistor.

Abstract translation: 具有电平移位电路，前级电路和后级电路的半导体器件。 电平移位电路将来自主电位系统的输入信号发送到不同于主电位系统的次级电位系统。 包括第一晶体管的前级电路接收由电平移位电路传送的栅极驱动信号。 包括具有与第一晶体管相同的沟道类型的第二晶体管的后级电路根据来自第一晶体管的输出信号驱动开关元件。 第一晶体管的阈值电压被设定为比第二晶体管的阈值电压低的值。