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公开(公告)号：US09698341B2
公开(公告)日：2017-07-04
申请号：US15081397
申请日：2016-03-25
CPC分类号： H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
摘要： A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using a plurality of masks. The magnetoresistive-based device includes magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer. In one embodiment, the method may include removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first mask, to form a first electrode and a first magnetic materials, respectively, and removing the tunnel barrier layer and the second magnetic materials layer unprotected by a second mask to form a tunnel barrier and second magnetic materials, and the second electrically conductive layer unprotected by the second mask to form, and a second electrode.
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公开(公告)号：US09697880B2
公开(公告)日：2017-07-04
申请号：US15193010
申请日：2016-06-25
发明人： Thomas Andre , Syed M. Alam , Chitra Subramanian
CPC分类号： G11C11/1675 , G11C7/02 , G11C7/065 , G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C2013/0057 , G11C2207/002
摘要： Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.
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公开(公告)号：US09697879B2
公开(公告)日：2017-07-04
申请号：US15366083
申请日：2016-12-01
CPC分类号： G11C11/1673 , G11C11/1659 , G11C11/1675
摘要： In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.
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公开(公告)号：USRE46428E1
公开(公告)日：2017-06-06
申请号：US15165600
申请日：2016-05-26
发明人： Phillip Mather , Jon Slaughter , Nicholas Rizzo
CPC分类号： H01L27/22 , B82Y25/00 , G01R33/093 , H01L43/08
摘要： Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).
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公开(公告)号：US20170069397A1
公开(公告)日：2017-03-09
申请号：US15356223
申请日：2016-11-18
CPC分类号： G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
摘要翻译： 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。
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公开(公告)号：US09542989B2
公开(公告)日：2017-01-10
申请号：US14887426
申请日：2015-10-20
发明人： Dietmar Gogl , Syed M. Alam , Thomas Andre
CPC分类号： G11C11/1675 , G11C5/147 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1697 , G11C13/0069 , G11C2213/79
摘要： A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.
摘要翻译： 电池偏置控制电路通过自动调节存储器阵列上的读/写路径的多个控制输入，使存储器单元（磁隧道结器件+晶体管）的读/写路径中的器件的性能最大化，而不会超过泄漏电流或可靠性限制 根据电源电压，温度和过程角变化的预定义配置，通过将任何特定参考参数配置文件应用于存储器阵列。
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公开(公告)号：US09529672B2
公开(公告)日：2016-12-27
申请号：US14496964
申请日：2014-09-25
发明人： Syed M. Alam , Thomas Andre
CPC分类号： H03M13/2906 , G06F11/1012 , G06F11/1076
摘要： A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction may be performed by the memory device on each of the ECC words associated with a page and a second level of error correction is performed on the data output by each of the input/output pads during a particular period of time.
摘要翻译： 存储器设备包括被配置为存储组织成多个ECC字的数据页的存储器阵列。 存储装置还包括用于与页面相关联的每个ECC字的至少一个输入/输出焊盘，使得存储器装置可以在与页面和第二级相关联的每个ECC字上执行第一级错误校正 在特定时间段内对每个输入/输出焊盘输出的数据执行纠错。
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公开(公告)号：US09502089B2
公开(公告)日：2016-11-22
申请号：US14502287
申请日：2014-09-30
CPC分类号： G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
摘要： In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
摘要翻译： 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。
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公开(公告)号：US20160320459A1
公开(公告)日：2016-11-03
申请号：US15134134
申请日：2016-04-20
IPC分类号： G01R33/09
CPC分类号： G01R33/091 , G01R33/096 , G01R33/098
摘要： A system, device, and method are disclosed for a tunneling magnetoresistance (TMR) magnetic sensor to effectively increase magnetic field measurement linearity and minimize cross-axis interference. The TMR magnetic sensor comprises a plurality of transducer legs, each having multiple sense elements. The TMR magnetic sensor comprises a plurality of built-in current lines located adjacent to each sense element. The current lines are routed such that two or more sense elements have magnetic responses that have opposing contributions from the cross-axis effect for a given field direction in each transducer leg within the TMR magnetic sensor. Therefore, the overall field response from each transducer leg is internally compensated and the TMR magnetic sensor has an output with minimal cross-axis interference.
摘要翻译： 公开了一种用于隧道磁阻（TMR）磁传感器的系统，装置和方法，以有效地增加磁场测量线性度并使跨轴干涉最小化。 TMR磁传感器包括多个换能器腿，每个具有多个感测元件。 TMR磁传感器包括位于每个感测元件附近的多个内置电流线。 当前线路由使得两个或更多个感测元件具有对TMR磁传感器内的每个换能器支路中的给定场方向的横轴效应具有相反贡献的磁响应。 因此，来自每个换能器支路的总体场响应被内部补偿，并且TMR磁传感器具有最小横轴干扰的输出。
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公开(公告)号：USRE46180E1
公开(公告)日：2016-10-18
申请号：US14638583
申请日：2015-03-04
发明人： Phillip Mather , Jon Slaughter , Nicholas Rizzo
CPC分类号： H01L27/22 , B82Y25/00 , G01R33/093 , H01L43/08
摘要： Three bridge circuits (101, 111, 121), each include magnetoresistive sensors coupled as a Wheatstone bridge (100) to sense a magnetic field (160) in three orthogonal directions (110, 120, 130) that are set with a single pinning material deposition and bulk wafer setting procedure. One of the three bridge circuits (121) includes a first magnetoresistive sensor (141) comprising a first sensing element (122) disposed on a pinned layer (126), the first sensing element (122) having first and second edges and first and second sides, and a first flux guide (132) disposed non-parallel to the first side of the substrate and having an end that is proximate to the first edge and on the first side of the first sensing element (122). An optional second flux guide (136) may be disposed non-parallel to the first side of the substrate and having an end that is proximate to the second edge and the second side of the first sensing element (122).
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