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公开(公告)号：US09893097B2
公开(公告)日：2018-02-13
申请号：US14762458
申请日：2015-06-17
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1288 , H01L27/124 , H01L27/1248 , H01L29/66765 , H01L29/78618 , H01L29/78678
Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming a gate of a thin-film transistor (TFT) of the LTPS array substrate on a substrate; forming a first insulating layer, a semiconductor layer, and a positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a second insulating layer on the substrate of the polycrystalline silicon layer; forming a source and a drain of the TFT on the second insulating layer so that the source and the drain is electrically connected to the polycrystalline silicon layer via a contact hole. The use of masks in types and in numbers in the LTPS technology will be reduced. So, both of the processes and the production costs are reduced.
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公开(公告)号：US20180040632A1
公开(公告)日：2018-02-08
申请号：US15023379
申请日：2016-02-25
Inventor： Chunqian ZHANG , Chao WANG , Jingfeng XUE
IPC: H01L27/12 , G02F1/1362 , H01L29/417 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/13454 , G02F1/136209 , G02F1/136227 , G02F1/136286 , G02F1/1368 , G02F2001/13685 , H01L21/77 , H01L27/12 , H01L27/1262 , H01L29/41733
Abstract: An array substrate includes a substrate, a buffer layer, a first shielding pattern, a passivation layer, a first semiconductor pattern, a gate insulating layer, a first gate pattern, an interlayer insulating layer, and two first source/drain electrode patterns. A first through hole and a second through hole are arranged on the array substrate. One of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern and the first shielding pattern through the first through hole. The other one of the first source/drain electrode patterns is electrically connected to the first semiconductor pattern through the second through hole and is insulated from the first shielding pattern. The present invention where the array substrate and the method of forming the array substrate are proposed is related to a top-gate design. The driving ability of the TFT driving circuit still improves without increasing the original processes and production costs.
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公开(公告)号：US20180040600A1
公开(公告)日：2018-02-08
申请号：US14912599
申请日：2016-01-29
Inventor： Yafeng Li , Jinfang Wu
IPC: H01L27/02 , H01L29/417 , G02F1/1362 , H01L27/12 , G09G3/36 , G02F1/1345
CPC classification number: H01L27/0207 , G02F1/13454 , G02F1/136213 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G2310/0283 , G09G2310/0286 , H01L27/1214 , H01L29/41733
Abstract: The present invention provides a GOA circuit based on LTPS semiconductor thin film transistor to control the voltage levels of the first node (Q(n)) and the second node (P(n)) with the forward scan direct current control signal (U2D) and the backward scan direct current control signal (D2U). The clock signal (CK(M)) is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit, and to realize the forward-backward scan of the GOA circuit. Moreover, the GOA unit of each stage comprises only ten thin film transistors, which is beneficial to reduce the layout space of the GOA circuit and to achieve the narrow frame design of the display device.
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公开(公告)号：US20180039359A1
公开(公告)日：2018-02-08
申请号：US14914660
申请日：2016-02-25
Inventor： Chunpeng GUO , Chun-hung Huang , Ying-chi WANG
CPC classification number: G06F3/0412 , G06F3/041 , G06F3/0416 , G06F3/044 , G09G3/3648 , G09G3/3688 , G09G2310/06 , G09G2320/0252 , G09G2330/021 , G09G2354/00
Abstract: A driving method for a liquid crystal panel is disclosed. Wherein, the driving method includes: (A) at a moment of switching from a normal display time stage to a touch scanning time stage in a current frame, applying a first over driving voltage to a common electrode of each pixel of a liquid crystal panel; and (B) at a moment of switching from the touch scanning time stage in the current frame to a normal display time stage of a next frame, applying a second over driving voltage to the common electrode of each pixel. According to the method described above a time that the common electrode reaches a present level voltage is shorten in order to effectively improve the poor display and touch problem caused by signal abnormality at moments of switching between a normal display and a touch scanning in an in-cell touch panel.
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635.发明申请公开(公告)号：US20180039142A1
公开(公告)日：2018-02-08
申请号：US14899104
申请日：2015-11-27
Inventor： Yuejun TANG
IPC: G02F1/1343 , G02F1/1335 , G02F1/1333 , G02F1/139 , G02F1/1341
CPC classification number: G02F1/134363 , G02F1/133308 , G02F1/133528 , G02F1/133707 , G02F1/1341 , G02F1/1343 , G02F1/134309 , G02F1/1393 , G02F2001/13793
Abstract: A blue-phase liquid crystal display panel includes a first substrate and a second substrate parallel to the first substrate. The first substrate is spaced apart from the second substrate. The first substrate includes a first base and a first electrode layer and a second electrode layer arranged close to one side of the second substrate. A first space is arranged between the first electrode layer and the second electrode layer, and a second space is arranged between the second electrode layer and the second substrate, and a channel is configured between the first space and the second space. The first electrode layer cooperatively operates with the second electrode layer to form an electrical field within the first space and a weight of the electrical field is parallel to the first substrate or the second substrate. In addition, a manufacturing method of the blue-phase liquid crystal display panel is disclosed.
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Patent Agency Ranking
公开(公告)号：US20180039105A1
公开(公告)日：2018-02-08
申请号：US14898819
申请日：2015-12-03
Inventor： Chang XIE
IPC: G02F1/136 , G02F1/1335 , G02F1/1343
CPC classification number: G02F1/136 , G02F1/133528 , G02F1/133553 , G02F1/133555 , G02F1/133605 , G02F1/1343
Abstract: A liquid crystal panel and a LCD are disclosed. The liquid crystal panel includes a first substrate and a second substrate parallel to each other, and a liquid crystal layer between the first substrate and the second substrate, wherein the first substrate comprises at least one reflective area and at least one transmission area arranged in an interleaved manner. A surface of the first substrate facing away the second substrate is configured with a metallic reflective layer of a wedged-shaped structure, the metallic reflective layer is arranged on the reflective area. A surface of the metallic reflective layer facing toward the liquid crystal layer is a plane, and a surface of the metallic reflective layer facing away the liquid crystal layer is a slope. A thickness of the metallic reflective layer has been gradually increased along a direction from the transmission area toward the reflective area.
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公开(公告)号：US09885933B1
公开(公告)日：2018-02-06
申请号：US15114848
申请日：2016-05-17
Inventor： Anshi Li
IPC: H01L27/14 , G02F1/1368 , G02F1/1362 , G02F1/1333 , G02F1/1343 , H01L29/45 , H01L29/417
CPC classification number: G02F1/1368 , G02F1/133345 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F2001/133357 , G02F2001/13685 , G02F2201/121 , G02F2201/123 , G02F2201/50 , G02F2202/104 , H01L27/12 , H01L29/41733 , H01L29/458
Abstract: The present invention provides a TFT array substrate and a manufacturing method thereof. The TFT array substrate has a source electrode (801) and a drain electrode (802), which each include, stacked from bottom to top, a first molybdenum layer (811), a first aluminum layer (812), a second aluminum layer (813), and a second molybdenum layer (814). The first aluminum layer (812) and the second aluminum layer (813) each have a surface including a plurality of spikes (8120) formed and distributed thereon. The spikes (8120) of the second aluminum layer (813) have a height greater than a height of the spikes (8120) of the first aluminum layer (812) such that the source electrode (801) and the drain electrode (802) each have an upper surface exhibiting a rough surface having irregularity comprising raised and recessed portion. Compared to a flat smooth surface that is involved in the prior art, the rough surface having irregularity comprising raised and recessed portions helps expand contact area between the drain electrode (802) and the pixel electrode (1200) so as to reduce contact impedance between a TFT and the pixel electrode and improve performance of a liquid crystal display panel.
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公开(公告)号：US20180033389A1
公开(公告)日：2018-02-01
申请号：US14913991
申请日：2016-01-28
Inventor： Yafeng Li , Jinfang Wu
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2092 , G09G3/3696 , G09G2300/0408 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G09G2320/0214 , G11C19/184 , G11C19/28
Abstract: The invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs (T12, T13) controlled by output ends (G(n−1), G(n+1)) of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT T12 connected through the fourth node (W1(n)) to source of first TFT (T1), the drain of first TFT (T1) connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT (T13) connected through the fifth node W2(n) to source of third TFT (T3), the drain of third TFT (T3) connected to output end of (n+1)-th GOA unit; the first and third TFTs (T1, T3) controlled respectively by the forward and backward scan DC control signals (U2D, D2U) to reduce leakage of twelfth TFT (T12) in forward scanning and leakage of thirteenth TFT (T13) in backward scanning. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
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公开(公告)号：US20180032183A1
公开(公告)日：2018-02-01
申请号：US14913997
申请日：2016-01-29
Inventor： Qiang Gong
IPC: G06F3/041
CPC classification number: G06F3/0412 , G06F3/041 , G06F3/0416 , G06F3/044
Abstract: The invention provides a touch driver circuit, by only using a select signal (Select) to control the operation of transport gates (TG1, TG2) to realize output of a valid pulse touch driver signal (TXH) and a constant low voltage signal (TXL). The circuit structure is simplified, and removes a plurality of elements and two control signals so as to reduce the layout space occupied by the touch driver circuit as well as reduced the border width of the touch display to realize narrow border design for touch display panel.
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公开(公告)号：US20180011370A1
公开(公告)日：2018-01-11
申请号：US15114850
申请日：2016-05-26
Inventor： Xiaojiang YU
IPC: G02F1/1335 , G02F1/1333 , G02F1/1343 , G02F1/1368 , G02F1/1341
CPC classification number: G02F1/133512 , G02F1/133345 , G02F1/133514 , G02F1/1341 , G02F1/134336 , G02F1/134363 , G02F1/13439 , G02F1/136277 , G02F1/1368 , G02F2001/133354 , G02F2001/134372 , G02F2001/134381 , G02F2201/121 , G02F2201/123 , G02F2202/104
Abstract: The present invention provides a display panel and a manufacture method thereof. By locating the matrix electrode corresponding to the black matrix on one side of the color film substrate, which is close to the liquid crystal layer, and because the matrix electrode is coupled to the common electrode signal, no voltage difference exists between the matrix electrode and the common electrode, and no matter in condition of being electrified or not electrified, the liquid crystal layer between the matrix electrode and the common electrode of the array substrate is not orientated and constantly appears in an opaque state so that no interference generates to light between adjacent pixels of the panel to eliminate the large view angle color washout of the panel and to improve the display quality of the LTPS display panel.
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