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公开(公告)号：US20210124206A1
公开(公告)日：2021-04-29
申请号：US16308483
申请日：2018-09-27
Inventor： Yafeng Li , Jinfang Wu
IPC: G02F1/1362 , G02F1/1333 , G02F1/1343 , G06F3/041
Abstract: The invention provides a TFT array substrate and LCD panel. the TFT array substrate comprises a first metal layer, a first interlayer insulating layer, a second metal layer, a second interlayer insulating layer and a third metal layer sequentially disposed above the substrate. The first, second and third metal layers comprise a plurality of first, second and third fanout lines in the fanout line area, respectively; two of the first, second, and third fanout lines are connected to the data lines, and the other is connected with the touch line; because the first interlayer insulating layer is disposed between the first and second fanout lines, and the second interlayer insulating layer is disposed between the third and second fanout lines, the first, second and third fanout lines can overlap, which can effectively reduce the fanout line area and help to achieve a narrow border.
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公开(公告)号：US09916805B2
公开(公告)日：2018-03-13
申请号：US14913991
申请日：2016-01-28
Inventor： Yafeng Li , Jinfang Wu
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2092 , G09G3/3696 , G09G2300/0408 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G09G2320/0214 , G11C19/184 , G11C19/28
Abstract: The invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs (T12, T13) controlled by output ends (G(n−1), G(n+1)) of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT T12 connected through the fourth node (W1(n)) to source of first TFT (T1), the drain of first TFT (T1) connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT (T13) connected through the fifth node W2(n) to source of third TFT (T3), the drain of third TFT (T3) connected to output end of (n+1)-th GOA unit; the first and third TFTs (T1, T3) controlled respectively by the forward and backward scan DC control signals (U2D, D2U) to reduce leakage of twelfth TFT (T12) in forward scanning and leakage of thirteenth TFT (T13) in backward scanning. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
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公开(公告)号：US10796656B1
公开(公告)日：2020-10-06
申请号：US16308813
申请日：2018-09-27
Inventor： Yafeng Li , Jinfang Wu
IPC: G09G3/36
Abstract: The invention provides a GOA circuit. The first node control module of the GOA circuit provided by the invention comprises a tenth TFT, an eleventh TFT and a twelfth TFT of N-type TFTs, when the voltage of the first node is high, the gate-to-source voltage difference of the twelfth TFT is the threshold voltage thereof, so that the drain-source voltage difference of the eleventh TFT is also the threshold voltage of the twelfth TFT, thereby making the resistance between the drain of the tenth TFT and the first node is extremely large, which can avoid the impact of leakage current generated by the tenth TFT on the voltage of the first node when the noise and coupling in the second node occurs, and to ensure the normal output of the scan signal.
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公开(公告)号：US09935094B2
公开(公告)日：2018-04-03
申请号：US14912599
申请日：2016-01-29
Inventor： Yafeng Li , Jinfang Wu
IPC: G09G3/36 , G11C19/28 , H01L27/02 , H01L29/417 , G02F1/1362 , H01L27/12 , G02F1/1345
CPC classification number: H01L27/0207 , G02F1/13454 , G02F1/136213 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G2310/0283 , G09G2310/0286 , H01L27/1214 , H01L29/41733
Abstract: The present invention provides a GOA circuit based on LTPS semiconductor thin film transistor to control the voltage levels of the first node (Q(n)) and the second node (P(n)) with the forward scan direct current control signal (U2D) and the backward scan direct current control signal (D2U). The clock signal (CK(M)) is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit, and to realize the forward-backward scan of the GOA circuit. Moreover, the GOA unit of each stage comprises only ten thin film transistors, which is beneficial to reduce the layout space of the GOA circuit and to achieve the narrow frame design of the display device.
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Patent Agency Ranking
公开(公告)号：US10714509B2
公开(公告)日：2020-07-14
申请号：US15744615
申请日：2017-12-21
Inventor： Yafeng Li , Jinfang Wu
Abstract: The present disclosure provides a display panel including a display area and a non-display area, a base substrate, a plurality of thin film transistors, a plurality of touch signal lines, a first test signal line area, an array substrate row driving circuit, a second test signal line area, a ground line area and an insulating layer. The thin film transistor includes a gate, a gate insulating layer, a source and a drain. The non-display area includes a first side and a second side; the array substrate row driving circuit respectively forms a first gap and a second gap with the first test signal line area and the second test signal line area, an orthographic projection of the ground line area on the base substrate is in the projection of the second test signal line area in the base substrate. The present disclosure also provides a display device.
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公开(公告)号：US10146080B1
公开(公告)日：2018-12-04
申请号：US15738031
申请日：2017-11-30
Inventor： Yafeng Li , Jinfang Wu
IPC: G02F1/1335 , G02F1/1343
Abstract: The present invention provides a method for manufacturing a display device includes providing an array substrate with a plurality of pixel unit areas formed on a surface thereof; defining a dividing line; dividing the pixel unit areas to a pixel calculating area, a predetermined displaying area, and a predetermined shielding area, and dividing the pixel calculating area to a first part and a second part by the dividing line; calculating areas of sub pixels according to light extraction efficiencies and effective light extraction areas of the sub pixels; forming a shielding layer according to the areas of the sub pixels.
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公开(公告)号：US20200320949A1
公开(公告)日：2020-10-08
申请号：US16308813
申请日：2018-09-27
Inventor： Yafeng Li , Jinfang Wu
IPC: G09G3/36
Abstract: The invention provides a GOA circuit. The first node control module of the GOA circuit provided by the invention comprises a tenth TFT, an eleventh TFT and a twelfth TFT of N-type TFTs, when the voltage of the first node is high, the gate-to-source voltage difference of the twelfth TFT is the threshold voltage thereof, so that the drain-source voltage difference of the eleventh TFT is also the threshold voltage of the twelfth TFT, thereby making the resistance between the drain of the tenth TFT and the first node is extremely large, which can avoid the impact of leakage current generated by the tenth TFT on the voltage of the first node when the noise and coupling in the second node occurs, and to ensure the normal output of the scan signal.
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公开(公告)号：US20180040600A1
公开(公告)日：2018-02-08
申请号：US14912599
申请日：2016-01-29
Inventor： Yafeng Li , Jinfang Wu
IPC: H01L27/02 , H01L29/417 , G02F1/1362 , H01L27/12 , G09G3/36 , G02F1/1345
CPC classification number: H01L27/0207 , G02F1/13454 , G02F1/136213 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G2310/0283 , G09G2310/0286 , H01L27/1214 , H01L29/41733
Abstract: The present invention provides a GOA circuit based on LTPS semiconductor thin film transistor to control the voltage levels of the first node (Q(n)) and the second node (P(n)) with the forward scan direct current control signal (U2D) and the backward scan direct current control signal (D2U). The clock signal (CK(M)) is merely in charge of the output of the GOA unit of corresponding stage, which can effectively reduce the loading of the clock signal. It ensures that the entire loading of the clock signal after the GOA units of multiple stages are coupled to promote the output stability of the GOA circuit, and to realize the forward-backward scan of the GOA circuit. Moreover, the GOA unit of each stage comprises only ten thin film transistors, which is beneficial to reduce the layout space of the GOA circuit and to achieve the narrow frame design of the display device.
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公开(公告)号：US20180033389A1
公开(公告)日：2018-02-01
申请号：US14913991
申请日：2016-01-28
Inventor： Yafeng Li , Jinfang Wu
CPC classification number: G09G3/3677 , G09G3/20 , G09G3/2092 , G09G3/3696 , G09G2300/0408 , G09G2310/0267 , G09G2310/0283 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G09G2320/0214 , G11C19/184 , G11C19/28
Abstract: The invention provides a GOA circuit for LTPS-TFT, by adding the twelfth and thirteenth TFTs (T12, T13) controlled by output ends (G(n−1), G(n+1)) of (n−1)-th and (n+1)-th GOA units, the drain of twelfth TFT T12 connected through the fourth node (W1(n)) to source of first TFT (T1), the drain of first TFT (T1) connected to output end of (n−1)-th GOA unit, the drain of thirteenth TFT (T13) connected through the fifth node W2(n) to source of third TFT (T3), the drain of third TFT (T3) connected to output end of (n+1)-th GOA unit; the first and third TFTs (T1, T3) controlled respectively by the forward and backward scan DC control signals (U2D, D2U) to reduce leakage of twelfth TFT (T12) in forward scanning and leakage of thirteenth TFT (T13) in backward scanning. As such, the leakage in key TFTs is reduced and GOA circuit stability is improved.
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