公开(公告)号：US20240363720A1

公开(公告)日：2024-10-31

申请号：US18459065

申请日：2023-08-31

Applicant: Texas Instruments Incorporated

Inventor： Henry Litzmann Edwards

IPC: H01L29/49 ,  H01L21/3215 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4983 ,  H01L21/32155 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66681 ,  H01L29/7816

Abstract: Disclosed examples include microelectronic devices, e.g. integrated circuits, that include a source region and a drain region extending into a semiconductor substrate, the semiconductor substrate having a second conductivity type, the source region and drain region having an opposite first conductivity type. A channel region having the second conductivity type extends between the source region and the drain region. A gate electrode over the channel region has a first portion and a second portion. The first portion has the second conductivity type and a first dopant concentration. The second portion extends from the first portion toward the source region and has the second conductivity type and a second higher dopant concentration.

公开(公告)号：US12132092B2

公开(公告)日：2024-10-29

申请号：US17743992

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/4238 ,  H01L21/76804 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/4933 ,  H01L29/6656

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

公开(公告)号：US20240355931A1

公开(公告)日：2024-10-24

申请号：US18028182

申请日：2022-05-11

Applicant: Beijing BOE Technology Development Co., Ltd. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wei GUO ,  Hu MENG

IPC: H01L29/786 ,  H01L21/449 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H10K85/20

CPC classification number: H01L29/78693 ,  H01L21/449 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  H10K85/211

Abstract: A thin film transistor includes: a substrate; a gate electrode; an active layer including a first active pattern and a second active pattern, where the first active pattern includes a first active sub-pattern, the first active sub-pattern comprises a first active region and a first source-drain contact region, the first source-drain contact region is connected to the second active pattern through the first active region, the first active pattern includes a material of at least one of a metal oxide semiconductor, low-temperature polycrystalline silicon, and amorphous silicon, and the second active pattern includes a material of a semiconductor carbon nanotube; a source electrode and a drain electrode spaced apart from each other and connected to the active layer; and a passivation layer on a side of the second active pattern distal to the substrate. A method for manufacturing the thin film transistor and a circuit are further provided.

公开(公告)号：US20240355908A1

公开(公告)日：2024-10-24

申请号：US18759649

申请日：2024-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Han CHUANG ,  Zhi-Chang LIN ,  Shih-Cheng CHEN ,  Jung-Hung CHANG ,  Chien Ning YAO ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66553 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4983 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A device includes a substrate, a first nanostructure channel above the substrate and a second nanostructure channel between the first nanostructure channel and the substrate. An inner spacer is between the first nanostructure channel and the second nanostructure channel. A gate structure abuts the first nanostructure channel, the second nanostructure channel and the inner spacer. A liner layer is between the inner spacer and the gate structure.

公开(公告)号：US20240347638A1

公开(公告)日：2024-10-17

申请号：US18301382

申请日：2023-04-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  David Charles Pritchard ,  Romain H.A. Feuillette ,  James P. Mazza ,  Hong Yu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/28123 ,  H01L29/1037 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed are a structure including a fin-type field effect transistor (FINFET) and a method. The FINFET includes first and second fins. An isolation structure is adjacent the outer sidewall of the first fin at a channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. A gate is adjacent the inner sidewall of the first fin at the channel region and extends over the first fin to the isolation structure. The gate is further adjacent an inner sidewall and top of the second fin at a channel region. In some embodiments, a second isolation structure is adjacent an outer sidewall of the second fin at the channel region and, optionally, fills a groove in the outer sidewall so the fin width is reduced. In this case, the gate extends over the second fin to the second isolation structure.

公开(公告)号：US20240347627A1

公开(公告)日：2024-10-17

申请号：US18755342

申请日：2024-06-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Lin LEE ,  Choh Fei YEAP ,  Da-Wen LIN ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66742 ,  H01L21/0259 ,  H01L21/28123 ,  H01L21/764 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/4991 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78621 ,  H01L29/78696

Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.

公开(公告)号：US20240347392A1

公开(公告)日：2024-10-17

申请号：US18753130

申请日：2024-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L21/285 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L27/0924 ,  H01L29/4966 ,  H01L21/28568

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US12119383B2

公开(公告)日：2024-10-15

申请号：US18174052

申请日：2023-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Mark D. Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli ,  Ajay Raman

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/49 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/401 ,  H01L21/76897 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/452 ,  H01L29/475 ,  H01L29/49 ,  H01L29/4983

Abstract: Disclosed are a transistor and a method for forming the transistor. The method includes concurrently forming gate and source/drain openings through an uppermost layer (i.e., a dielectric layer) in a stack of layers. The method can further include: depositing and patterning gate conductor material so that a first gate section is in the gate opening and a second gate section is above the gate opening and so that the source/drain openings are exposed; extending the depth of the source/drain openings; and depositing and patterning source/drain conductor material so that a first source/drain section is in each source/drain opening and a second source/drain section is above each source/drain opening. Alternatively, the method can include: forming a plug in the gate opening and sidewall spacers in the source/drain openings; extending the depth of source/drain openings; depositing and patterning the source/drain conductor material; and subsequently depositing and patterning the gate conductor material.

公开(公告)号：US20240339498A1

公开(公告)日：2024-10-10

申请号：US18478280

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Ryeol YOO

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/4975 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a first epitaxial pattern connected to first bridge patterns sequentially stacked on a first region and penetrating through a first gate structure, the first epitaxial layer on a side of the first gate structure and including a first conductivity type impurity, a first silicide pattern on the first epitaxial pattern and overlapping the first bridge patterns in the first direction, a second epitaxial pattern connected to second bridge patterns sequentially stacked on a second region and penetrating through a second gate structure, the second epitaxial layer on a side of the second gate structure and including a second conductivity type impurity different from the first conductivity type impurity, and a second silicide pattern on the second epitaxial pattern and overlapping the second bridge patterns in the third direction, wherein the first silicide pattern and the second silicide pattern have stress properties different from each other.

公开(公告)号：US20240339456A1

公开(公告)日：2024-10-10

申请号：US18746818

申请日：2024-06-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Lin Huang ,  Lung-Kun Chu ,  Chung-Wei Hsu ,  Jia-Ni Yu ,  Kuo-Cheng Chiang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823857 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78696

Abstract: A semiconductor device according to an embodiment includes a first gate-all-around (GAA) transistor and a second GAA transistor. The first GAA transistor includes a first plurality of channel members, a first interfacial layer over the first plurality of channel members, a first hafnium-containing dielectric layer over the first interfacial layer, and a metal gate electrode layer over the first hafnium-containing dielectric layer. The second GAA transistor includes a second plurality of channel members, a second interfacial layer over the second plurality of channel members, a second hafnium-containing dielectric layer over the second interfacial layer, and the metal gate electrode layer over the second hafnium-containing dielectric layer. A first thickness of the first interfacial layer is greater than a second thickness of the second interfacial layer. A third thickness of the first hafnium-containing dielectric layer is smaller than a fourth thickness of the second hafnium-containing dielectric layer.