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    Planar dielectric isolated integrated circuits
    56.
    发明授权
    Planar dielectric isolated integrated circuits 失效
    平面电介质隔离集成电路

    公开(公告)号：US3766438A

    公开(公告)日：1973-10-16

    申请号：US3766438D

    申请日：1970-05-26

    Applicant: IBM

    Inventor： CASTRUCCI P ,  MASON J

    IPC: H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L19/00

    CPC classification number: H01L21/31111 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/31055 ,  H01L21/76297 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S438/945 ,  Y10S438/977

    Abstract: A method for fabricating dielectric isolated integrated devices which allows the formation of a truly planar surface. The method includes etching isolation channels in a semiconductor substrate through a suitable mask. The mask pattern is designed to enhance deeper etching at certain locations in the isolation channels. A dielectric layer is formed over the exposed surfaces of the isolation channels and a semiconductor material is grown in the channels. The deeper etched locations which are now filled with dielectric isolation are used as a depth guide in the formation of a dielectric layer from the semiconductor substrate surface opposite to the one from which the etching took place. The depth guide can be used in either a deep etch or lap-back process. The last isolation step is then to continue the dielectric layer past the depth guide to the major portion of the isolation channels to produce the fully isolated islands of semiconductor material in the semiconductor substrate.

    Methods for making transistor structures
    58.
    发明授权
    Methods for making transistor structures 失效
    制造晶体管结构的方法

    公开(公告)号：US3761785A

    公开(公告)日：1973-09-25

    申请号：US3761785D

    申请日：1971-04-23

    Applicant: BELL TELEPHONE LABOR INC

    Inventor： PRUNIAUX B

    IPC: H01L21/00 ,  H01L21/306 ,  H01L29/08 ,  H01L29/78 ,  H01L29/812 ,  H01L11/00

    CPC classification number: H01L29/8122 ,  H01L21/00 ,  H01L21/30608 ,  H01L29/0847 ,  H01L29/7827 ,  Y10S148/037 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S438/944

    Abstract: A high frequency field effect transistor is made by first epitaxially growing semiconductor channel and drain layers over a source layer. An oxide layer is formed on the upper drain layer which acts as a mask during etching of the epitaxial layers. Anisotropic etching of the semiconductor forms a mesa configuration of the channel and drain layers which is overlapped by the upper oxide layer. Metal is then evaporated onto the mesa from a point opposite the oxide layer. The overhanging oxide layer masks part of the mesa, particularly the drain layer, to define precisely the area covered by the evaporated gate contact, as required for high frequency operation. Other embodiments are also described.

    Abstract translation: 通过在源极层上首先外延生长半导体沟道和漏极层来制造高频场效应晶体管。 在蚀刻外延层期间作为掩模的上漏极层上形成氧化物层。 半导体的各向异性蚀刻形成与上部氧化物层重叠的沟道层和漏极层的台面构造。 然后将金属从与氧化物层相对的点蒸发到台面上。 突出的氧化物层掩盖台面的一部分，特别是漏极层，以精确地限定由蒸发的栅极接触覆盖的区域，这是高频操作所需要的。 还描述了其它实施例。

    Silicon semiconductor device processing
    59.
    发明授权
    Silicon semiconductor device processing 失效
    硅半导体器件加工

    公开(公告)号：US3751314A

    公开(公告)日：1973-08-07

    申请号：US3751314D

    申请日：1971-07-01

    Applicant: BELL TELEPHONE LABOR INC

    Inventor： RANKEL L

    IPC: H01L21/225 ,  H01L21/316 ,  H01L7/50 ,  H01L7/44

    CPC classification number: H01L21/02129 ,  H01L21/02271 ,  H01L21/2255 ,  H01L21/31625 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/106

    Abstract: Silicon semiconductor devices containing boron doped regions are produced using borosilicate glass as a doping source and silica glass as a masking layer. After the device is heated to produce boron diffusion into the silicon surface, a preferential etchant is used to remove the borosilicate glass while leaving the masking layer substantially in place for use in subsequent processing steps. The etchant is an aqueous solution of HF and HNO3.

    Abstract translation: 使用硼硅酸盐玻璃作为掺杂源和石英玻璃作为掩蔽层来制造含有硼掺杂区的硅半导体器件。 在器件被加热以产生硼扩散到硅表面之后，使用优选的蚀刻剂去除硼硅酸盐玻璃，同时使掩蔽层基本上在适当位置用于随后的处理步骤。 蚀刻剂是HF和HNO3的水溶液。

    Poly-silicon electrodes for c-igfets
    60.
    发明授权
    Poly-silicon electrodes for c-igfets 失效
    用于C-IGFET的聚硅电极

    公开(公告)号：US3750268A

    公开(公告)日：1973-08-07

    申请号：US3750268D

    申请日：1971-09-10

    Applicant: MOTOROLA INC

    Inventor： WANG R

    IPC: H01L29/78 ,  H01L21/00 ,  H01L21/336 ,  H01L23/485 ,  H01L27/092 ,  H01L29/00 ,  H01L11/14 ,  B01J

    CPC classification number: H01L23/485 ,  H01L21/00 ,  H01L27/0927 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/051 ,  Y10S148/122 ,  H01L2924/00

    Abstract: Poly-silicon electrodes are provided for use with source and drain regions of insulated gate field-effect transistors as well as a method for contacting silicon gate devices utilizing polysilicon electrodes and a single etching step. The single etching step obviates the use of an additional masking operation for forming preohmic holes in the vicinity of the source and drain regions for the device. The provision of preohmic holes at the source and drain regions necessitates large area source and drain regions so as to permit clearance for the metallization through preohmic holes. These large areas decrease packing density. The subject method however permits high density packing of the silicon gate devices because small area source and drain regions and small area electrodes can be used. Because of the use of poly-silicon electrodes, the process allows the probing of the chip at intermediate stages in device fabrication. This allows the elimination of those chips which have not satisfied design limitations at an intermediate step in the fabrication process. In the process the source and drain regions and the electrodes are doped simultaneously in a diffusion step. In this diffusion process part of the source and drain regions are diffused through that portion of the poly-silicon contact extending over the source or drain region. In this manner ohmic contact is made between the electrodes and the underlying source or drain regions.

    Abstract translation: 提供了用于绝缘栅场效应晶体管的源极和漏极区域的多硅电极以及利用多晶硅电极和单个蚀刻步骤接触硅栅极器件的方法。 单个蚀刻步骤避免了使用用于在器件的源极和漏极区域附近形成预氧化孔的附加掩模操作。 在源极和漏极区域提供预氧化空穴需要大的面积源极和漏极区域，以便允许通过预氧化孔的金属化间隙。 这些大面积降低了包装密度。 然而，本方法允许硅栅极器件的高密度堆积，因为可以使用小面积的源极和漏极区域以及小面积的电极。 由于使用多晶硅电极，该工艺允许在器件制造的中间阶段探测芯片。 这允许消除在制造过程中的中间步骤中不满足设计限制的那些芯片。 在该过程中，源极和漏极区域和电极在扩散步骤中同时掺杂。 在该扩散处理中，源极和漏极区域的一部分通过在源极或漏极区域上延伸的多晶硅接触部分扩散。 以这种方式，在电极和下面的源极或漏极区域之间形成欧姆接触。

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