公开(公告)号：US09401403B2

公开(公告)日：2016-07-26

申请号：US14636163

申请日：2015-03-02

申请人： Panasonic Intellectual Property Management Co., Ltd.

发明人： Hidekazu Umeda ,  Masahiro Ishida ,  Tetsuzo Ueda ,  Daisuke Ueda

IPC分类号： H01L21/02 ,  H01L21/762 ,  H01L29/205 ,  H01L29/778 ,  H01L29/86 ,  H01L29/15 ,  H01L29/20 ,  H01L29/36

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/7786 ,  H01L29/86

摘要： A nitride semiconductor structure of the present disclosure comprises a semiconductor substrate, and a layer formed over the semiconductor substrate and comprising plural nitride semiconductor layers. The semiconductor substrate has, from a side thereof near the layer comprising the plural nitride semiconductor layers, a surface region and an internal region in this order. The surface region has a resistivity of 0.1 Ωcm or more, and the internal region has a resistivity of 1000 Ωcm or more.

摘要翻译： 本公开的氮化物半导体结构包括半导体衬底和形成在半导体衬底上并包括多个氮化物半导体层的层。 半导体衬底从其包括多个氮化物半导体层的层的一侧开始依次具有表面区域和内部区域。 表面区域的电阻率为0.1Ωcm以上，内部区域的电阻率为1000Ωcm以上。

公开(公告)号：US20160211411A1

公开(公告)日：2016-07-21

申请号：US14681327

申请日：2015-04-08

申请人： Trustees of Boston University

发明人： Yitao Liao ,  Theodore D. Moustakas

IPC分类号： H01L33/14 ,  H01L33/32 ,  H01L33/06

CPC分类号： H01L33/32 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0259 ,  H01L21/02625 ,  H01L33/007 ,  H01L33/025 ,  H01L33/06

摘要： A method of growing an AlGaN semiconductor material utilizes an excess of Ga above the stoichiometric amount typically used. The excess Ga results in the formation of band structure potential fluctuations that improve the efficiency of radiative recombination and increase light generation of optoelectronic devices, in particular ultraviolet light emitting diodes, made using the method. Several improvements in UV LED design and performance are also provided for use together with the excess Ga growth method. Devices made with the method can be used for water purification, surface sterilization, communications, and data storage and retrieval.

摘要翻译： 生长AlGaN半导体材料的方法利用高于通常使用的化学计量量的过量的Ga。 多余的Ga导致形成带结构电位波动，从而提高辐射复合的效率并增加使用该方法制造的光电器件，特别是紫外发光二极管的光产生。 还提供了紫外LED设计和性能的几项改进，以及多余的Ga生长方法。 使用该方法制造的设备可用于水净化，表面灭菌，通信和数据存储和检索。

公开(公告)号：US09397258B2

公开(公告)日：2016-07-19

申请号：US14814044

申请日：2015-07-30

申请人： Soitec

发明人： Chantal Arena ,  Jean-Philippe Debray ,  Richard Scott Kern

IPC分类号： H01L31/0328 ,  H01L27/15 ,  H01L21/00 ,  H01L33/06 ,  H01L33/18 ,  H01L33/00 ,  H01L33/08 ,  H01L33/12 ,  H01L33/32 ,  H01L33/14 ,  H01L21/02

CPC分类号： H01L33/06 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L33/0062 ,  H01L33/0066 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/08 ,  H01L33/12 ,  H01L33/145 ,  H01L33/18 ,  H01L33/32 ,  H01L33/325 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014

摘要： Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

摘要翻译： 半导体结构包括多层InGaN之间的有源区。 有源区可以至少基本上由InGaN组成。 多层InGaN包括至少一个阱层以及至少一个靠近至少一个阱层的势垒层。 形成半导体结构的方法包括生长这样的InGaN层以形成诸如LED的发光器件的有源区。 照明装置包括这样的LED。

公开(公告)号：US09337023B1

公开(公告)日：2016-05-10

申请号：US14570703

申请日：2014-12-15

申请人： Texas Instruments Incorporated

发明人： Qhalid Fareed ,  Asad Mahmood Haider

IPC分类号： H01L29/15 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC分类号： H01L21/02505 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7781 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/78

摘要： A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

摘要翻译： 制造用于晶体管的多层外延缓冲层堆叠的方法包括在衬底上沉积缓冲层。 第一空穴IIIA-N层被沉积在衬底上，然后在第一空穴IIIA-N层上沉积第一基本无空隙的IIIA-N层。 第一高粗糙度组IIIA-N层沉积在第一基本无空隙的IIIA-N族第一层上，并且第一基本上平滑的IIIA-N层沉积在第一高粗糙度IIIA-N层上。 然后将至少一个IIIA-N族表面层沉积在第一基本上平滑的IIIA-N层上。

公开(公告)号：US09330907B2

公开(公告)日：2016-05-03

申请号：US14512158

申请日：2014-10-10

申请人： The Board of Trustees of the Leland Stanford Junior University

发明人： Robert Chen ,  James S. Harris, Jr. ,  Suyog Gupta

IPC分类号： H01L21/02 ,  H01L21/00 ,  H01L29/161 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01S5/34 ,  H01L21/3065 ,  B81C1/00 ,  H01S5/10

CPC分类号： H01L21/02535 ,  B81C1/00111 ,  B81C1/00571 ,  B81C2201/014 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/161 ,  H01S5/1075 ,  H01S5/3427

摘要： Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.

公开(公告)号：US09330906B2

公开(公告)日：2016-05-03

申请号：US14266900

申请日：2014-05-01

申请人： Sensor Electronic Technology, Inc.

发明人： Maxim S. Shatalov ,  Jinwei Yang ,  Wenhong Sun ,  Rakesh Jain ,  Michael Shur ,  Remigijus Gaska

IPC分类号： H01L31/00 ,  H01L21/02 ,  H01L29/20 ,  H01L33/00 ,  H01L33/12

CPC分类号： H01L29/158 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0265 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12

摘要： A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

公开(公告)号：US09318324B2

公开(公告)日：2016-04-19

申请号：US14656937

申请日：2015-03-13

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Chiharu Ota ,  Ryosuke Iijima ,  Tatsuo Shimizu ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L21/02 ,  H01L21/265 ,  H01L29/16

CPC分类号： H01L21/02529 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02507 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/26513 ,  H01L29/1608

摘要： A manufacturing method of an SiC epitaxial substrate of an embodiment includes performing a first and a second process alternately to form an n type SiC layer, the first process forming a first SiC layer with an epitaxial growth process by using a first source gas containing an n type impurity, and the second process forming a second SiC layer with an epitaxial growth process by using a second source gas containing the n type impurity, the second source gas having a higher atomic ratio between C (carbon) and Si (silicon) (C/Si) than that of the first source gas, a thickness of the second SiC layer being smaller than a thickness of the first SiC layer.

摘要翻译： 实施例的SiC外延衬底的制造方法包括交替地执行第一和第二工艺以形成n型SiC层，所述第一工艺通过使用包含n型SiC的第一源气体，通过外延生长工艺形成第一SiC层 并且通过使用包含n型杂质的第二源气体，通过外延生长工艺形成第二SiC层的第二工艺，第二源气体在C（碳）和Si（硅）（C）之间具有较高的原子比 / Si），第二SiC层的厚度小于第一SiC层的厚度。

公开(公告)号：US20160104777A1

公开(公告)日：2016-04-14

申请号：US14967261

申请日：2015-12-11

申请人： Yu-Chen Chang

发明人： Yu-Chen Chang

IPC分类号： H01L29/12 ,  H01L29/20 ,  H01L33/32 ,  H01L33/04 ,  H01L33/12 ,  H01L33/30 ,  H01L29/15 ,  H01L29/207

CPC分类号： H01L29/127 ,  B82Y20/00 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/0259 ,  H01L21/02631 ,  H01L29/0665 ,  H01L29/155 ,  H01L29/157 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/207 ,  H01L31/035218 ,  H01L33/0062 ,  H01L33/04 ,  H01L33/06 ,  H01L33/12 ,  H01L33/30 ,  H01L33/305 ,  H01L33/32 ,  H01L33/325 ,  Y02E10/544

摘要： A semiconductor device comprises a substrate and quantum dots, wherein a peak emission of the quantum dots has a FWHM of less than 20 meV when the semiconductor is measured at a temperature of 4 Kelvin.

公开(公告)号：US20160093491A1

公开(公告)日：2016-03-31

申请号：US14868428

申请日：2015-09-29

申请人： University of North Texas

发明人： Wonbong Choi ,  Nitin Choudhary

IPC分类号： H01L21/02 ,  H01L29/786 ,  H01L29/66

CPC分类号： H01L21/02568 ,  H01L21/02444 ,  H01L21/02485 ,  H01L21/02507 ,  H01L21/02527 ,  H01L21/0259 ,  H01L21/02614 ,  H01L21/02631 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78681 ,  H01L29/78696

摘要： The invention is for fabricating large-area, thickness-modulated MoS2, varying from single to few layer MoS2 films on various substrates using a combination of magnetron sputtering followed by chemical vapor deposition. The thickness dependent energy bandgap engineering and surface induced polarity change is disclosed.

摘要翻译： 本发明用于制造大面积，厚度调制的MoS2，其使用磁控溅射，然后化学气相沉积的组合，在各种衬底上从单层到几层MoS 2膜变化。 公开了厚度依赖能带隙工程和表面诱发极性变化。

公开(公告)号：US20160064482A1

公开(公告)日：2016-03-03

申请号：US14935406

申请日：2015-11-07

申请人： International Business Machines Corporation

发明人： Pouya Hashemi ,  Ali Khakifirooz ,  Alexander Reznicek

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

CPC分类号： H01L29/78618 ,  B82Y10/00 ,  H01L21/02507 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

摘要： A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.