公开(公告)号：US11374122B2

公开(公告)日：2022-06-28

申请号：US16996963

申请日：2020-08-19

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Katsuhisa Tanaka ,  Ryosuke Iijima

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/761 ,  H01L21/04 ,  H02P27/06 ,  B66B11/04 ,  B60L50/51 ,  B61C3/00

摘要： A semiconductor device of an embodiment includes an element region and a termination region surrounding the element region. The element region includes a gate trench, a first silicon carbide region of n-type, a second silicon carbide region of p-type on the first silicon carbide region, a third silicon carbide region of n-type on the second silicon carbide region, and a fourth silicon carbide region of p-type sandwiches the first silicon carbide region and the second silicon carbide region with the gate trench, the fourth silicon carbide region being deeper than the gate trench. The termination region includes a first trench surrounding the element region, and a fifth silicon carbide region of p-type between the first trench and the first silicon carbide region, the fifth silicon carbide region same or shallower than the fourth silicon carbide region. The semiconductor device includes a gate electrode, a first electrode, and a second electrode.

公开(公告)号：US11276751B2

公开(公告)日：2022-03-15

申请号：US16797037

申请日：2020-02-21

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shinya Kyogoku ,  Toshiyuki Oshima ,  Ryosuke Iijima

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  B66B11/04 ,  H02P27/06 ,  B60K1/00 ,  B60R16/023 ,  B61C3/00

摘要： A semiconductor device of an embodiment includes a silicon carbide layer having first and second plane, the silicon carbide layer including trench having a first portion and a second portion, the second portion having a width smaller than the first portion, an n-type first silicon carbide region, a p-type second silicon carbide region between the first silicon carbide region and the first plane, a p-type third silicon carbide region between the second silicon carbide region and the first plane and having a p-type impurity concentration lower than the second silicon carbide region, an n-type fourth silicon carbide region between the third silicon carbide region and the first plane, and an n-type fifth silicon carbide region between the second portion and the second silicon carbide region and having an n-type impurity concentration higher than the first silicon carbide region; and a gate electrode in the trench.

公开(公告)号：US11121249B2

公开(公告)日：2021-09-14

申请号：US16798814

申请日：2020-02-24

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shinya Kyogoku ,  Katsuhisa Tanaka ,  Ryosuke Iijima

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  B66B1/30 ,  B60L13/00 ,  H02M7/537 ,  B60R16/03

摘要： A semiconductor device of an embodiment includes a silicon carbide layer having a first plane and a second plane and includes a trench located on a first plane side and has a first region and a second region, a first silicon carbide region of an n-type, a second silicon carbide region of a p-type between the first silicon carbide region and the first plane, a third silicon carbide region of the n-type between the second silicon carbide region and the first plane, and a fourth silicon carbide region of the p-type between the second region and the first silicon carbide region; a gate electrode in the first region; a first electrode on the first plane side of the silicon carbide layer, a part of the first electrode is located in the second region and is in contact with the third and the fourth silicon carbide region; and a second electrode.

公开(公告)号：US20210066467A1

公开(公告)日：2021-03-04

申请号：US16789535

申请日：2020-02-13

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Tatsuo Shimizu ,  Ryosuke Iijima

IPC分类号： H01L29/423 ,  H01L29/16 ,  H01L29/10

摘要： A semiconductor device according to an embodiment includes a gate electrode, a gate insulating layer, and a silicon carbide layer. The silicon carbide layer includes at least one first element selected from the group consisting of S, Se, Te, Ti, Zr, Hf, V, Nb, Ta, Cr, Mo, and W. The first distance between a first position and an interface between the gate insulating layer and the silicon carbide layer is equal to or less than 20 nm, and the first position is a position where a concentration of the first element is maximized. The second distance between a second position and the interface is equal to or less than 20 nm, second position is a position where a concentration of the first element is 1/10 of a concentration of the first element at the first position, and the second position is farther from the interface than the first position.

公开(公告)号：US10424640B2

公开(公告)日：2019-09-24

申请号：US14813692

申请日：2015-07-30

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Ryosuke Iijima ,  Johji Nishio ,  Teruyuki Ohashi

IPC分类号： H01L29/08 ,  H01L21/04 ,  H01L29/66 ,  H01L21/02 ,  H01L21/225 ,  H01L29/40 ,  H01L29/43 ,  H01L29/78 ,  H01L29/868

摘要： A semiconductor device according to an embodiment includes a SiC layer, an electrode electrically connected to the SiC layer and an impurity region provided between the SiC layer and the electrode. The impurity region includes first position and second position, the first position having highest concentration of an impurity in the impurity region, the highest concentration being not lower than 1×1020 cm−3 and not higher than 5×1022 cm−3, the second position having concentration of the impurity one digit lower than the highest concentration, the first position being between the electrode and the second position, a distance between the first position and the second position being 50 nm or shorter.

公开(公告)号：US09825121B2

公开(公告)日：2017-11-21

申请号：US14970767

申请日：2015-12-16

申请人： Kabushiki Kaisha Toshiba

发明人： Ryosuke Iijima ,  Keiko Ariyoshi ,  Tatsuo Shimizu ,  Kazuto Takao ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7835

摘要： A semiconductor device of the embodiment includes an SiC layer of 4H—SiC structure having a surface inclined at an angle from 0 degree to 30 degrees relative to {11-20} face or {1-100} face, a gate electrode, a gate insulating film provided between the surface and the gate electrode, a n-type first SiC region provided in the SiC layer, a n-type second SiC region provided in the SiC layer, a channel forming region provided in the SiC layer between the first SiC region and the second SiC region, the channel forming region provided adjacent to the surface, and the channel forming region having a direction inclined at an angle from 60 degrees to 90 degrees relative to a direction or a direction.

公开(公告)号：US09812411B2

公开(公告)日：2017-11-07

申请号：US15235404

申请日：2016-08-12

申请人： Kabushiki Kaisha Toshiba

发明人： Kentaro Ikeda ,  Kazuto Takao ,  Ryosuke Iijima

IPC分类号： H01L23/64 ,  H01L29/16 ,  H01L29/78 ,  H01L49/02 ,  H01L23/373 ,  H01L23/58 ,  H01L23/427 ,  H01L23/62 ,  H02M7/00

CPC分类号： H01L23/645 ,  H01L23/3735 ,  H01L23/427 ,  H01L23/585 ,  H01L23/62 ,  H01L25/072 ,  H01L25/074 ,  H01L28/40 ,  H01L29/1608 ,  H01L29/7805 ,  H02M7/003

摘要： A semiconductor device of an embodiment includes a first electrode, a second electrode facing the first electrode, an alternating-current electrode, a first switching element provided between the first electrode and the alternating-current electrode, and a second switching element provided between the second electrode and the alternating-current electrode. The first switching element and the second switching element are electrically connected in series between the first electrode and the second electrode, and the alternating-current electrode is electrically connected between the first switching element and the second switching element.

公开(公告)号：US09793354B2

公开(公告)日：2017-10-17

申请号：US14619306

申请日：2015-02-11

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Ryosuke Iijima ,  Takashi Shinohe

IPC分类号： H01L21/336 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/1608 ,  H01L21/0485 ,  H01L29/41725 ,  H01L29/45 ,  H01L29/66068

摘要： A semiconductor device according to an embodiment includes: a first electrode; a SiC semiconductor layer including n-type semiconductor; and a second electrode including a SiC metallic region made of metal in contact with the SiC semiconductor layer, the SiC metallic region provided on a side of the SiC semiconductor layer opposite to the first electrode, the SiC metallic region containing at least one element selected from the group of Mg (magnesium), Ca (calcium), Sr (strontium), Ba (barium), Sc (scandium), Y (yttrium), La (lanthanum), and lanthanoid (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu).

公开(公告)号：US09716186B2

公开(公告)日：2017-07-25

申请号：US14875787

申请日：2015-10-06

申请人： Kabushiki Kaisha Toshiba

发明人： Johji Nishio ,  Tatsuo Shimizu ,  Ryosuke Iijima ,  Teruyuki Ohashi ,  Kazuto Takao ,  Takashi Shinohe

IPC分类号： H01L29/868 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/32 ,  H01L29/861

CPC分类号： H01L29/868 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/8611

摘要： A semiconductor device manufacturing method according to an embodiment includes: forming an n-type SiC layer on a SiC substrate; forming a p-type impurity region at one side of the SiC layer; exposing other side of the SiC layer by removing at least part of the SiC substrate; implanting carbon (C) ions into exposed part of the SiC layer; performing a heat treatment; forming a first electrode on the p-type impurity region; and forming a second electrode on the exposed part of the SiC layer.

公开(公告)号：US09490327B2

公开(公告)日：2016-11-08

申请号：US14619595

申请日：2015-02-11

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo Shimizu ,  Ryosuke Iijima ,  Takashi Shinohe

IPC分类号： H01L29/15 ,  H01L29/16 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/223

CPC分类号： H01L29/1608 ,  H01L21/046 ,  H01L21/223 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7833

摘要： A semiconductor device according to an embodiment includes: a semiconductor substrate; an n-type SiC layer provided on one side of the semiconductor substrate; a p-type first SiC region provided in the n-type SiC layer; a metallic second SiC region provided in the p-type first SiC region, the second SiC region containing at least one element selected from the group of Mg, Ca, Sr, Ba, Sc, Y, La, and lanthanoid; a gate electrode; a gate insulating film provided between the gate electrode and the n-type SiC layer, the gate insulating film provided between the gate electrode and the first SiC region; a first electrode provided on the second SiC region; and a second electrode provided on a side of the semiconductor substrate opposite to the n-type SiC layer.

摘要翻译： 根据实施例的半导体器件包括：半导体衬底; 设置在半导体衬底一侧的n型SiC层; 设置在n型SiC层中的p型第一SiC区域; 设置在p型第一SiC区域中的金属第二SiC区域，所述第二SiC区域含有选自Mg，Ca，Sr，Ba，Sc，Y，La和镧系元素中的至少一种元素; 栅电极; 设置在所述栅极电极和所述n型SiC层之间的栅极绝缘膜，所述栅极绝缘膜设置在所述栅电极和所述第一SiC区域之间; 设置在所述第二SiC区域上的第一电极; 以及设置在与n型SiC层相对的半导体衬底侧的第二电极。