公开(公告)号：US11996294B2

公开(公告)日：2024-05-28

申请号：US17983560

申请日：2022-11-09

Applicant: Applied Materials, Inc.

Inventor： Alvaro Garcia De Gorordo ,  Zhonghua Yao ,  Sunil Srinivasan ,  Sang Wook Park

IPC: H01L21/306 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L21/3065 ,  H01L21/02112 ,  H01L21/02263 ,  H01L21/0234 ,  H01L21/02348 ,  B81C2201/0138 ,  H01L21/0228 ,  H01L21/30655 ,  H01L21/31116

Abstract: The present disclosure generally relates to substrate processing methods, such as etching methods with noble gases at low temperatures. In an aspect, the method includes exposing a substrate, a first layer comprising a gas, and a fluorine-containing layer to energy to form a passivation layer while maintaining the substrate at conditions encompassing a triple point temperature of the gas, the substrate positioned in a processing region of a processing chamber. The method further includes etching the substrate with ions.

公开(公告)号：US20240172410A1

公开(公告)日：2024-05-23

申请号：US18547151

申请日：2023-04-20

Applicant: ChangXin Memory Technologies, Inc.

Inventor： Tao DOU

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/762

CPC classification number: H10B12/02 ,  H01L21/0228 ,  H01L21/76224 ,  H10B12/488

Abstract: A method of manufacturing a semiconductor structure is disclosed. The semiconductor structure includes a transistor area, which includes a first source-drain area and a word line region. The method includes forming an active layer on a substrate, and the active layer of the transistor region includes a plurality of active structures. A dummy word line structure covering the active structure of the same layer is formed in the first source drain region and the word line region. The first isolation layers arranged alternately with the dummy word line structures in the third direction are formed. Then the dummy word line structure is removed. An initial dielectric layer is formed on the surface of the active structure of the first source-drain region and the word line region. An initial word line is formed on the surface of the initial dielectric layer. The initial word line and the initial dielectric layer located in the first source and drain region are removed.

公开(公告)号：US20240170612A1

公开(公告)日：2024-05-23

申请号：US18423986

申请日：2024-01-26

Applicant: Silanna UV Technologies Pte Ltd

Inventor： Petar Atanackovic

IPC: H01L33/26 ,  H01L21/02 ,  H01L23/66 ,  H01L27/15 ,  H01L29/15 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34

CPC classification number: H01L33/26 ,  H01L21/02178 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02458 ,  H01L21/02507 ,  H01L23/66 ,  H01L27/15 ,  H01L29/151 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7869 ,  H01L33/002 ,  H01L33/007 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/62 ,  H01S5/34 ,  H01L29/7786 ,  H01L2223/6627

Abstract: In some embodiments, the techniques described herein relate to an epitaxial oxide transistor. The transistor can include: a substrate; a channel layer including a first epitaxial semiconductor layer on the substrate; a gate layer including a second epitaxial semiconductor layer on the first epitaxial semiconductor layer; a source electrode and a drain electrode coupled to the channel layer; and a gate electrode coupled to the gate layer. The first epitaxial semiconductor layer can include a first polar oxide material and the second epitaxial semiconductor layer can include a second polar oxide material. The first polar oxide material and the second polar oxide material can include cation-polar surfaces oriented towards or away from the substrate, and the second polar oxide material can include a wider bandgap than the first polar oxide material.

公开(公告)号：US20240170279A1

公开(公告)日：2024-05-23

申请号：US18355369

申请日：2023-07-19

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Hongzhu ZHENG ,  Jian WANG ,  Yunqing DAI ,  Wenzhan ZHOU

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/02186 ,  H01L21/0228 ,  H01L21/823821 ,  H01L27/092

Abstract: The present application provides a method for fabricating multiple work function layers, including: forming the first to the nth transistor gates with notches; forming a blocking layer in the notches; depositing the first work function layer and removing the first work function layer on the first to the (n−1)th transistor gates; depositing a second work function layer; removing the second work function layer on the first to the (n−2)th transistor gates; depositing a third work function layer on the blocking layer on the first to the (n−2)th transistor gates and the second work function layer on the (n−1)th and nth transistor gates; removing the third work function layer on the first to (n−3)th transistor gates; depositing the third to the (n−1)th work function layers by analogy until only the blocking layer exists on the last transistor gate, herein the thickness of the third to the (n−1)th work function layers decreases sequentially and gradually.

公开(公告)号：US20240170277A1

公开(公告)日：2024-05-23

申请号：US18201453

申请日：2023-05-24

Applicant: Shanghai Huali Integrated Circuit Corporation

Inventor： Yenxia HAO

IPC: H01L21/02 ,  C23C16/36 ,  C23C16/455

CPC classification number: H01L21/02126 ,  C23C16/36 ,  C23C16/45536 ,  H01L21/0228

Abstract: The present application provides a method for increasing the process window to avoid bridging between the device's contact hole and gate, including: placing a semiconductor structure containing a gate structure in a reaction cavity, wherein reaction gases fed sequentially into the reaction cavity include the first reaction gas containing Si and Cl, a second reaction gas containing C and a third reaction gas containing O. Thus, a first film containing Cl is formed on the sidewalls of the gate structure. Further, a fourth reaction gas containing H is fed into the reaction cavity, after the fourth reaction gas completes reaction with Cl in the first film, a second film is formed on the sidewalls of the gate. A fifth gas containing N is then fed into the reaction cavity, which reacts with the second film to form a third film on the spacer of the gate structure.

公开(公告)号：US11990375B2

公开(公告)日：2024-05-21

申请号：US17852716

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wen Huang ,  Jaming Chang ,  Kai Hung Cheng ,  Chia-Hui Lin ,  Jei Ming Chen

IPC: H01L27/148 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.

公开(公告)号：US11984398B2

公开(公告)日：2024-05-14

申请号：US17465744

申请日：2021-09-02

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Yexiao Yu ,  Zhongming Liu ,  Jia Fang

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L23/528 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/32139

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method of the semiconductor structure comprises: providing a substrate, comprising a polysilicon layer, a first conductive layer, a first dielectric layer, a mask layer, and a sacrificial layer sequentially formed thereon, wherein the sacrificial layer has a plurality of first trenches distributed at intervals; forming a first insulating layer on the sacrificial layer; forming a protective layer, the protective layer only covering a surface of the first insulating layer above the top surface of the sacrificial layer; removing the protective layer, part of the first insulating layer, the sacrificial layer, and part of the mask layer to form a first pattern layer; and removing part of the first dielectric layer, part of the first conductive layer, and part of the polysilicon layer by using the first pattern layer as a mask to form a BL structure.

公开(公告)号：US20240154021A1

公开(公告)日：2024-05-09

申请号：US18090875

申请日：2022-12-29

Applicant: NATIONAL SUN YAT-SEN UNIVERSITY

Inventor： TING-CHANG CHANG ,  Wei-Chen Huang ,  Shih-Kai Lin ,  Yong-Ci Zhang ,  Sheng-Yao Chou ,  Chung-Wei Wu ,  Po-Hsun Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L21/0228 ,  H01L21/02439 ,  H01L21/02521 ,  H01L29/2003 ,  H01L29/7786

Abstract: A p-GaN high-electron-mobility transistor (HEMT) includes a buffer layer stacked on a substrate, a channel layer stacked on the buffer layer, a supply layer stacked on the channel layer, a doped layer stacked on the supply layer, and a hydrogen barrier layer covering the supply layer and the doped layer. A source and a drain are electrically connected to the channel layer and the supply layer, respectively. A gate is located on the doped layer. The hydrogen barrier layer is doped with fluorine.

公开(公告)号：US20240153762A1

公开(公告)日：2024-05-09

申请号：US18283728

申请日：2022-03-11

Applicant: Paragraf Limited

Inventor： Sebastian DIXON ,  Jaspreet KAINTH ,  Robert JAGT

IPC: H01L21/02

CPC classification number: H01L21/02527 ,  H01L21/02008 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/02488 ,  H01L21/02502

Abstract: A wafer for the CVD growth of uniform graphene and method of manufacture thereof There is provided a wafer for the CVD growth of uniform graphene at a temperature in excess of 700° C., the wafer comprising in order: a planar silicon substrate, an insulating layer provided across the silicon substrate, and a barrier layer provided across the insulating layer, wherein the insulating layer is a silicon nitride and/or aluminium nitride layer, and wherein the barrier layer has a constant thickness of 50 nm or less and provides a growth surface for the CVD growth of uniform graphene.

公开(公告)号：US20240145571A1

公开(公告)日：2024-05-02

申请号：US18150259

申请日：2023-01-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Ting Lin ,  Yu-Ming Hsiang ,  Wei-Chih Wen ,  Yin-Hao Wu ,  Wu-Wei Tsai ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/0228 ,  H01L29/66969 ,  H01L29/78391 ,  H10B51/30

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.