公开(公告)号：US20240028438A1

公开(公告)日：2024-01-25

申请号：US17868427

申请日：2022-07-19

Applicant: DELL PRODUCTS L.P.

Inventor： Isaac Q. Wang ,  Stuart Allen Berke ,  Jordan Chin

IPC: G06F11/07 ,  G06F13/42 ,  G06F9/448

CPC classification number: G06F11/0772 ,  G06F11/0778 ,  G06F13/4221 ,  G06F9/4498

Abstract: An information handling system includes a processor and a Compute express link (CXL) device. The CXL device is coupled to the processor by a Peripheral Component Interface-Express (PCIe)/CXL link. The processor initiates a link training on the PCIe/CXL link, determines that the PCIe/CXL link failed to train to a first data rate, trains the PCIe/CXL link to a second data rate in response to determining that the PCIe/CXL link failed to train to the first data rate, and operates the CXL device in a CXL mode in response to training the PCIe/CXL link to the second data rate.

公开(公告)号：US11876702B2

公开(公告)日：2024-01-16

申请号：US17594815

申请日：2020-03-23

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Abdulla M. Bataineh ,  Thomas L. Court ,  Hess M. Hodge

IPC: G06F13/14 ,  H04L45/02 ,  H04L45/028 ,  H04L45/125 ,  H04L45/00 ,  H04L45/122 ,  H04L47/76 ,  H04L49/15 ,  H04L49/00 ,  H04L69/40 ,  H04L47/10 ,  H04L49/9005 ,  H04L47/34 ,  H04L67/1097 ,  G06F13/16 ,  H04L45/021 ,  H04L47/12 ,  G06F13/42 ,  H04L47/2441 ,  H04L47/30 ,  H04L47/62 ,  H04L47/24 ,  H04L49/90 ,  G06F13/38 ,  G06F13/40 ,  H04L45/745 ,  H04L47/2483 ,  H04L47/629 ,  H04L47/80 ,  H04L49/101 ,  H04L45/12 ,  H04L47/122 ,  G06F12/1036 ,  G06F15/173 ,  H04L43/10 ,  H04L45/42 ,  H04L47/11 ,  G06F12/0862 ,  G06F12/1045 ,  H04L47/32 ,  G06F9/54 ,  G06F9/50 ,  H04L47/22 ,  H04L47/52 ,  H04L47/6275 ,  H04L45/24 ,  H04L45/7453 ,  H04L45/16 ,  H04L69/22 ,  H04L47/762 ,  H04L47/78 ,  H04L47/20 ,  H04L49/9047 ,  H04L1/00 ,  H04L43/0876 ,  H04L47/2466 ,  H04L47/625 ,  H04L69/28

CPC classification number: H04L45/02 ,  G06F9/505 ,  G06F9/546 ,  G06F12/0862 ,  G06F12/1036 ,  G06F12/1063 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F15/17331 ,  H04L1/0083 ,  H04L43/0876 ,  H04L43/10 ,  H04L45/021 ,  H04L45/028 ,  H04L45/122 ,  H04L45/123 ,  H04L45/125 ,  H04L45/16 ,  H04L45/20 ,  H04L45/22 ,  H04L45/24 ,  H04L45/38 ,  H04L45/42 ,  H04L45/46 ,  H04L45/566 ,  H04L45/70 ,  H04L45/745 ,  H04L45/7453 ,  H04L47/11 ,  H04L47/12 ,  H04L47/122 ,  H04L47/18 ,  H04L47/20 ,  H04L47/22 ,  H04L47/24 ,  H04L47/2441 ,  H04L47/2466 ,  H04L47/2483 ,  H04L47/30 ,  H04L47/32 ,  H04L47/323 ,  H04L47/34 ,  H04L47/39 ,  H04L47/52 ,  H04L47/621 ,  H04L47/626 ,  H04L47/629 ,  H04L47/6235 ,  H04L47/6275 ,  H04L47/76 ,  H04L47/762 ,  H04L47/781 ,  H04L47/80 ,  H04L49/101 ,  H04L49/15 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04L49/90 ,  H04L49/9005 ,  H04L49/9021 ,  H04L49/9036 ,  H04L49/9047 ,  H04L67/1097 ,  H04L69/22 ,  H04L69/40 ,  G06F2212/50 ,  G06F2213/0026 ,  G06F2213/3808 ,  H04L69/28

Abstract: A network interface controller (NIC) capable of facilitating efficient memory address translation is provided. The NIC can be equipped with a host interface, a cache, and an address translation unit (ATU). During operation, the ATU can determine an operating mode. The operating mode can indicate whether the ATU is to perform a memory address translation at the NIC. The ATU can then determine whether a memory address indicated in the memory access request is available in the cache. If the memory address is not available in the cache, the ATU can perform an operation on the memory address based on the operating mode.

公开(公告)号：US11875172B2

公开(公告)日：2024-01-16

申请号：US17107568

申请日：2020-11-30

Applicant: VMware LLC

Inventor： Renaud B. Voltz

IPC: G06F9/455 ,  G06F9/54 ,  G06F13/42 ,  G06F9/4401 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/4406 ,  G06F9/45541 ,  G06F9/547 ,  G06F13/4221 ,  G06F9/5077 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45591 ,  G06F2009/45595 ,  G06F2213/0026

Abstract: Some embodiments provide a method for operating a physical server in a network. The method stores multiple copies of a virtual machine (VM) image at a network-accessible storage. The method uses a first copy of the VM image as a virtual disk to execute a VM on a hypervisor of a first physical computing device. The method uses a second copy of the VM image as a virtual disk accessible via a smart network interface controller (NIC) of a second physical computing device to execute an operating system of the second physical computing device.

公开(公告)号：US11874689B2

公开(公告)日：2024-01-16

申请号：US17749133

申请日：2022-05-19

Applicant: SK hynix Inc.

Inventor： Yong Tae Jeon ,  Ji Woon Yang ,  Dae Sik Park

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A Peripheral Component Interconnect Express (PCIe) interface device may include a PCIe layer, a link training module, a PCIe register, and a PCIe controller. The PCIe layer may perform communication between a host and a Direct Memory Access (DMA) device. The link training module may perform a link training for the host. The PCIe register may store data information on the PCIe layer. The PCIe controller may switch an operating clock from a PCIe clock, generated based on a reference clock, to an internal clock, process data of the PCIe layer on the basis of the internal clock, and control the link training module to recover a link for the host, when a reset signal received from the host is asserted or the reference clock is off.

公开(公告)号：US11868279B2

公开(公告)日：2024-01-09

申请号：US17952430

申请日：2022-09-26

Applicant: Liqid Inc.

Inventor： Christopher R. Long ,  Andrew Rudolph Heyd ,  Brenden Rust

IPC: G06F13/10 ,  G06F13/42 ,  G06F13/40 ,  G06F13/00

CPC classification number: G06F13/102 ,  G06F13/4022 ,  G06F13/4221

Abstract: Designs for a rackmount chassis having multiple card slots are presented herein. In one example, an apparatus includes a chassis configured to mount into a server rack, including a plurality of peripheral card slots, and a plurality of status lights configured to provide indications of operational status for an associated slot. The chassis further includes switch circuitry, including at least three switch elements, configured to couple the slots, wherein a first portion of ports on each of the switch elements is coupled to corresponding slots, a second portion of the ports on each of the switch elements is coupled to external ports of the chassis, and a third portion of the ports on each of the switch elements is coupled to at least another among the switch elements. The chassis may further include a plurality of external ports on the chassis communicatively coupled to the slots through the switch circuitry.

公开(公告)号：US11868209B2

公开(公告)日：2024-01-09

申请号：US18046453

申请日：2022-10-13

Applicant: Ampere Computing LLC

Inventor： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC: G06F11/00 ,  G06F11/10 ,  G06F13/42

CPC classification number: G06F11/1004 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

公开(公告)号：US20240004823A1

公开(公告)日：2024-01-04

申请号：US17855106

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Brian Mitchell ,  George D. Azevedo

IPC: G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/4282 ,  G06F2213/0028 ,  G06F2213/0026

Abstract: An apparatus and method for efficiently supporting multiple peripheral communication protocols in a computing system. A computing system includes multiple servers with one or more of the servers using multiple connectors for connecting to multiple peripheral devices such as data storage devices. At least one of the connectors is able to support multiple communication protocols, rather than a single communication protocol. A processor of the server determines a peripheral device has been attached to a connector that supports multiple communication protocols, and the processor determines whether one of the multiple communication protocols supported by the particular connector matches the attached peripheral device's communication protocol. If so, the processor configures the connector with the matching communication protocol. Otherwise, the processor generates an indication that specifies that there is no match.

公开(公告)号：US20240004822A1

公开(公告)日：2024-01-04

申请号：US17854490

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： George D. Azevedo ,  Peter Malcolm Barnes ,  Michael J. Tresidder

IPC: G06F13/40 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/409 ,  G06F13/4221 ,  G06F15/7807

Abstract: Systems, apparatuses, and methods for automatic firmware provision of high speed serializer/deserializer (SERDES) links are disclosed. A system on chip (SoC) includes one or more microcontrollers, a programmable interconnect, a plurality of physical layer engines, and a plurality of SERDES lanes. The programmable interconnect and the plurality of SERDES lanes are able to support communication protocols for interfaces such as PCIE, SATA, Ethernet, and others. On bootup, the SoC receives a custom specification of how the plurality of SERDES lanes are to be configured. The one or more microcontrollers generate a mapping for the programmable interconnect based on the specification. The mapping is used to configure the programmable interconnect to match the specification. The result is the programmable interconnect connecting the plurality of SERDES lanes to the appropriate physical layer circuits to implement the desired configuration.

公开(公告)号：US11853179B1

公开(公告)日：2023-12-26

申请号：US16728338

申请日：2019-12-27

Applicant: TELEDYNE LECROY, INC.

Inventor： Aaron Masters ,  Kevin Lemay ,  Chuck Tuffli

IPC: G06F13/28 ,  G06F11/22 ,  G06F13/42

CPC classification number: G06F11/221 ,  G06F13/28 ,  G06F13/4221 ,  G06F2213/0026

Abstract: A method for detecting a Direct Memory Access (DMA) memory address violation when testing PCIe devices is disclosed. The method for detecting a DMA memory address violation when testing PCIe devices applies to unintentional and intentional accesses of memory space outside of an area in memory specified by the device driver developed for the device.

公开(公告)号：US20230409507A1

公开(公告)日：2023-12-21

申请号：US18333293

申请日：2023-06-12

Applicant: Zenlayer Innovation LLC

Inventor： Jun Xu ,  Seagle Yang

IPC: G06F13/42 ,  H04L9/40 ,  G06F9/4401

CPC classification number: G06F13/4221 ,  H04L63/0442 ,  G06F9/4411 ,  H04L2212/00 ,  G06F2213/0024 ,  G06F2213/0026

Abstract: Methods and systems are disclosed to aggregate traffic from multiple server devices through a peripheral component interconnect (PCI) hosting device. In one embodiment, the PCI hosting device comprises a network interface to couple the PCI hosting device to a network, a plurality of PCI interfaces, a processing circuit to forward packets, and a power supply to supply power to the PCI interfaces independently from the plurality of server devices. Each of the PCI interfaces is designed to be coupled to one server device to the PCI hosting device, which is registered as a first PCI board of a first server device through a first PCI interface and as a second PCI board of a second server device through a second PCI interface, and the PCI hosting device is designed to forward packets between the network interface and the first server device, and the network interface and the second server device.