公开(公告)号：US20220407813A1

公开(公告)日：2022-12-22

申请号：US17349379

申请日：2021-06-16

申请人： Ampere Computing LLC

发明人： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC分类号： H04L12/863 ,  H04L1/20 ,  H04L1/00

摘要： Apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based system. The processor-based system includes a transmit circuit configured to generate an implied sequence number for each entry to be transmitted as a packet. The transmit circuit is configured to generate a packet to be transmitted based on an entry, wherein the packet including the payload information and the transmit check value based on the implied sequence number and associated with the entry. In this manner, including an individual sequence number with every transmitted packet may be reduced or avoided to reduce or avoid consuming bandwidth on the communications interface, as the bits used by the sequence number could ordinarily be used for data transmission instead. A receiver circuit is configured to receive the transmitted packet including the payload and the transmit check value, wherein the transmit check value is based on the transmit sequence number.

公开(公告)号：US11481270B1

公开(公告)日：2022-10-25

申请号：US17349601

申请日：2021-06-16

申请人： Ampere Computing LLC

发明人： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC分类号： G06F11/10 ,  G06F13/42

摘要： The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

公开(公告)号：US11868209B2

公开(公告)日：2024-01-09

申请号：US18046453

申请日：2022-10-13

申请人： Ampere Computing LLC

发明人： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F13/42

CPC分类号： G06F11/1004 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

摘要： The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.