公开(公告)号：US20240004577A1

公开(公告)日：2024-01-04

申请号：US17856299

申请日：2022-07-01

申请人： Ampere Computing LLC

发明人： Massimo Sutera ,  Sandeep Brahmadathan ,  Nagi Aboulenein ,  Brian Thomas Chase ,  James Edward Casteel ,  Kha Minh Huynh ,  Vung Thanh Huynh

IPC分类号： G06F3/06

CPC分类号： G06F3/0656 ,  G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

摘要： Apparatus and methods for extending functionality of memory controllers in a processor-based device are disclosed herein. In one aspect, a processor-based device provides a memory access intercept circuit that is communicatively coupled to a memory controller and a memory device. The memory access intercept circuit is configured to receive a memory write request that is directed to and received by the memory controller, and generates a write transaction identifier (ID) for the memory write request. The memory access intercept circuit then generates proxy write data containing the write transaction ID, and sends the proxy write data to the memory controller. The memory access intercept circuit subsequently intercepts the actual write data directed to the memory controller, and stores the write data in a write data buffer in association with the write transaction ID.

公开(公告)号：US20220407813A1

公开(公告)日：2022-12-22

申请号：US17349379

申请日：2021-06-16

申请人： Ampere Computing LLC

发明人： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC分类号： H04L12/863 ,  H04L1/20 ,  H04L1/00

摘要： Apparatuses, systems, and methods for implied sequence numbering of transactions in a processor-based system. The processor-based system includes a transmit circuit configured to generate an implied sequence number for each entry to be transmitted as a packet. The transmit circuit is configured to generate a packet to be transmitted based on an entry, wherein the packet including the payload information and the transmit check value based on the implied sequence number and associated with the entry. In this manner, including an individual sequence number with every transmitted packet may be reduced or avoided to reduce or avoid consuming bandwidth on the communications interface, as the bits used by the sequence number could ordinarily be used for data transmission instead. A receiver circuit is configured to receive the transmitted packet including the payload and the transmit check value, wherein the transmit check value is based on the transmit sequence number.

公开(公告)号：US20230315571A1

公开(公告)日：2023-10-05

申请号：US17707636

申请日：2022-03-29

申请人： Ampere Computing LLC

发明人： Massimo Sutera ,  Nagi Aboulenein ,  Sandeep Brahmadathan

IPC分类号： G06F11/10 ,  G06F12/02

CPC分类号： G06F11/108 ,  G06F12/0246

摘要： A codeword read from memory includes data blocks including data and supplemental blocks including error correction code (ECC) symbols for detecting and correcting data errors. Metadata can be stored in the supplemental blocks to increase memory utilization but using bits of the supplemental blocks for metadata leaves too few bits remaining for the ECC symbols. To maintain error protection, the supplemental blocks include ECC symbols to protect a first data portion of the codeword and parity bits configured to protect a second data portion of the codeword. Errors in the first data portion can be located and corrected using the ECC symbols. Errors in the second data portion can be detected by the parity. For example, the first data portion is encoded based on the second data portion, so locations of parity errors correspond to locations of symbol errors, and parity errors can be corrected.

公开(公告)号：US11868209B2

公开(公告)日：2024-01-09

申请号：US18046453

申请日：2022-10-13

申请人： Ampere Computing LLC

发明人： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F13/42

CPC分类号： G06F11/1004 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0024 ,  G06F2213/0026

摘要： The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.

公开(公告)号：US20240220356A1

公开(公告)日：2024-07-04

申请号：US18608820

申请日：2024-03-18

申请人： Ampere Computing LLC

发明人： Massimo Sutera ,  Nagi Aboulenein ,  Sandeep Brahmadathan

IPC分类号： G06F11/10

CPC分类号： G06F11/102

摘要： A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

公开(公告)号：US20230315565A1

公开(公告)日：2023-10-05

申请号：US17707660

申请日：2022-03-29

申请人： Ampere Computing LLC

发明人： Massimo Sutera ,  Nagi Aboulenein ,  Sandeep Brahmadathan

IPC分类号： G06F11/10

CPC分类号： G06F11/102

摘要： A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

公开(公告)号：US12019565B2

公开(公告)日：2024-06-25

申请号：US17810244

申请日：2022-06-30

申请人： Ampere Computing LLC

发明人： Sandeep Brahmadathan ,  Danh La

IPC分类号： G06F13/12 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F13/126 ,  G06F13/1673 ,  G06F13/4291

摘要： Methods and systems for an advanced initialization bus (AIB) are presented. In an aspect, an AIB master sends, to an AIB slave, a serial clock over a first signal line, and performs a read operation with the AIB slave. Performing the read operation comprises sending a read command to the AIB slave via a bus comprising at least one bidirectional input/output (I/O) channel, each I/O channel having its own respective signal line, sending a read address to the AIB slave via the bus, receiving a copy of the serial clock from the AIB slave over a second signal line, and latching read data provided by the AIB slave via the bus into a read buffer using the copy of the serial clock as a data strobe. Thus, the AIB master latches the read data provided by the AIB slave using a read strobe also provided by the AIB slave.

公开(公告)号：US11934263B2

公开(公告)日：2024-03-19

申请号：US17707660

申请日：2022-03-29

申请人： Ampere Computing LLC

发明人： Massimo Sutera ,  Nagi Aboulenein ,  Sandeep Brahmadathan

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/102

摘要： A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

公开(公告)号：US11481270B1

公开(公告)日：2022-10-25

申请号：US17349601

申请日：2021-06-16

申请人： Ampere Computing LLC

发明人： Matthew Robert Erler ,  Robert James Safranek ,  Robert Joseph Toepfer ,  Sandeep Brahmadathan ,  Shailendra Ramrao Chavan ,  Jonglih Yu

IPC分类号： G06F11/10 ,  G06F13/42

摘要： The system or device may build one or more data packets by dividing a given payload for a packet into data blocks and inserting data checks for each data block sequentially into the packet payload. The device may generate, for each of the data blocks, a corresponding data check block corresponding to data in each data block. The device may send or arrange the data blocks and the corresponding data check blocks such that each of the data blocks is followed by the corresponding error check block in the packet. Using the corresponding check block, each of the data blocks is independently verifiable, so that the data blocks may be used upon receipt, even if the payload is not completely received.