公开(公告)号：US20180284187A1

公开(公告)日：2018-10-04

申请号：US15471390

申请日：2017-03-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Ivor G. Barber ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Tien-Yu Lee ,  Henley Liu ,  David M. Mahoney ,  Mohsen H. Mardi

IPC: G01R31/28

CPC classification number: G01R31/2891 ,  G01R31/2889

Abstract: Integrated (IC) package testing systems and methods for testing an IC package are provided herein that accommodate IC packages having different die heights. In one example, the IC package testing system includes a test fixture base, a socket, and a test fixture head. The socket is disposed on the test fixture base and configured to receive an IC package for testing. The test fixture head is movable towards and away from the base. The test fixture head includes a base plate and a plurality of independently movable pushers. The plurality of pushers are configured to engage the IC package disposed the socket.

公开(公告)号：US20180144963A1

公开(公告)日：2018-05-24

申请号：US15360187

申请日：2016-11-23

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Mohsen H. Mardi ,  Tien-Yu Lee ,  Ivor G. Barber ,  Cheang-Whang Chang ,  Jaspreet Singh Gandhi

IPC: H01L21/673 ,  H01L21/67 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/67333 ,  H01L21/4853 ,  H01L21/4882 ,  H01L21/563 ,  H01L21/67109 ,  H01L23/3185 ,  H01L23/3675 ,  H01L24/16 ,  H01L2224/16227

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

公开(公告)号：US09831104B1

公开(公告)日：2017-11-28

申请号：US14935011

申请日：2015-11-06

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L21/56 ,  H01L21/67 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/67126 ,  H01L23/3142 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: Techniques for providing a unified underfill and encapsulation for integrated circuit die assemblies. These techniques include a molding technique that includes dipping a die assembly including a substrate and one or more dies into a chamber having molding material, sealing the chamber, and lowering pressure in the chamber to coax the molding material into space between the die(s) and substrate. The use of this molding technique, as contrasted with a capillary underfill technique in which underfill material is laid down adjacent dies and fills space under the die via capillary action, provides several benefits. One benefit is that the molding material can include a higher silica particle filler content (% by weight) than the material for the capillary underfill technique, which improves CTE. Another benefit is that various design constraints related to, for example, warpage and partial underfill are eliminated or improved.

公开(公告)号：US09627329B1

公开(公告)日：2017-04-18

申请号：US14175920

申请日：2014-02-07

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2224/73204

Abstract: A TSV interposer having a reinforced edge and methods for fabricating an IC package utilizing the same are provided. In one embodiment, a chip package includes an interposer having a wiring layer and a die disposed on a surface of the interposer. The die is electrically connected to the wiring layer of the interposer. A die underfill material is disposed between the interposer and the die. The die underfill material at least partially covers a side of the die that extends away from the surface of the interposer. Stiffening material is disposed in contact with the interposer and the die underfill material.

公开(公告)号：US20170092619A1

公开(公告)日：2017-03-30

申请号：US14867349

申请日：2015-09-28

Applicant: Xilinx, Inc.

Inventor： Gamal Refai-Ahmed ,  Tien-Yu Lee ,  Ferdinand F. Fernandez ,  Suresh Ramalingam ,  Ivor G. Barber ,  Inderjit Singh ,  Nael Zohni

IPC: H01L25/065 ,  H01L23/06 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00 ,  H01L23/10 ,  H01L23/367

CPC classification number: H01L23/373 ,  H01L21/4882 ,  H01L23/04 ,  H01L23/16 ,  H01L23/367 ,  H01L23/40 ,  H01L23/4006 ,  H01L23/473 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method and apparatus are provided which improve heat transfer between a lid and an IC die of an IC (chip) package. In one embodiment, a chip package is provided that includes a first IC die, a package substrate, a lid and a stiffener. The first IC die is coupled to the package substrate. The stiffener is coupled to the package substrate and circumscribes the first IC die. The lid has a first surface and a second surface. The second surface faces away from the first surface and towards the first IC die. The second surface of the lid is conductively coupled to the IC die, while the lid is mechanically decoupled from the stiffener.

公开(公告)号：US09245865B1

公开(公告)日：2016-01-26

申请号：US14571173

申请日：2014-12-15

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L31/12 ,  H01L21/50 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3142 ,  H01L21/563 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0655 ,  H01L29/0657 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14132 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/32013 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83365 ,  H01L2224/8385 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K1/0271 ,  H05K1/141 ,  H05K1/144 ,  H05K3/28 ,  H05K3/3436 ,  H05K2201/09036 ,  H05K2201/2072 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/05442

Abstract: In an example, an integrated circuit (IC) package includes a package substrate, an IC die, solder bumps, a first plurality of trenches, and underfill material. The IC die includes a front surface and a back surface, the front surface facing the package substrate and including a conductive interface. The solder bumps couple the conductive interface to the package substrate. The first plurality of trenches includes at least one trench proximate each corner of the IC die formed in the front surface of the IC die in an area between the conductive interface and a perimeter of the IC die. The underfill material is disposed between the front surface of the IC die and the package substrate, the underfill material being in contact with the first plurality of trenches.

Abstract translation: 在一个示例中，集成电路（IC）封装包括封装基板，IC管芯，焊料凸块，第一多个沟槽和底部填充材料。 IC芯片包括前表面和后表面，前表面面向封装衬底并且包括导电界面。 焊料凸块将导电界面耦合到封装衬底。 所述第一多个沟槽包括在所述IC芯片的前表面中形成于所述IC裸片的所述导电界面和所述IC芯片的周边之间的区域中的靠近所述IC管芯的每个拐角的至少一个沟槽。 底部填充材料设置在IC管芯的前表面和封装衬底之间，底部填充材料与第一多个沟槽接触。

公开(公告)号：US09224697B1

公开(公告)日：2015-12-29

申请号：US14100749

申请日：2013-12-09

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

IPC: H01L21/00 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/16 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/27 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An integrated circuit includes an interposer die having a surface, a first die mechanically and electrically attached to the surface of the interposer die, and a second die only mechanically attached to the surface of the interposer die using a die attach adhesive.

Abstract translation: 集成电路包括具有表面的内插器模具，机械地和电连接到插入器模具的表面的第一模具，以及仅使用芯片附着粘合剂机械地附接到插入件模具的表面的第二模具。

公开(公告)号：US08946884B2

公开(公告)日：2015-02-03

申请号：US13791819

申请日：2013-03-08

Applicant: Xilinx, Inc.

Inventor： Woon-Seong Kwon ,  Suresh Ramalingam ,  Namhoon Kim ,  Joong-Ho Kim

IPC: H01L23/12 ,  H01L23/48 ,  H01L23/485 ,  H01L21/768 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H05K3/28 ,  H05K3/46 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L21/76802 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81005 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18161 ,  H05K3/28 ,  H05K3/4682

Abstract: A substrate-less interposer for a stacked silicon interconnect technology (SSIT) product, includes: a plurality of metallization layers, at least a bottom most layer of the metallization layers comprising a plurality of metal segments, wherein each of the plurality of metal segments is formed between a top surface and a bottom surface of the bottom most layer of the metallization layers, and the metal segments are separated by dielectric material in the bottom most layer; and a dielectric layer formed on the bottom surface of the bottom most layer, wherein the dielectric layer includes one or more openings for providing contact to the plurality of metal segments in the bottom most layer.

Abstract translation: 一种用于层叠硅互连技术（SSIT）产品的无衬底插入件包括：多个金属化层，至少最底层的金属化层包括多个金属段，其中多个金属段中的每一个均为 形成在金属化层的最底层的顶表面和底表面之间，并且金属段由最底层中的电介质材料分离; 以及形成在最底层的底表面上的电介质层，其中介电层包括用于提供与最底层中的多个金属段接触的一个或多个开口。