公开(公告)号：US20160133529A1

公开(公告)日：2016-05-12

申请号：US14981604

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sandeep Kumar Goel

IPC: H01L21/66 ,  H01L21/683 ,  H01L21/822 ,  G01R31/3187

CPC classification number: H01L22/20 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/3187 ,  H01L21/6835 ,  H01L21/822 ,  H01L22/32 ,  H01L2221/6835

Abstract: A method for testing a monolithic stacked integrated circuit (IC) is provided. The method includes receiving a layer of the IC. The layer has a first surface and a second surface, and the layer includes a substrate. The method further includes attaching probe pads to the first surface, and applying a first fault testing to the IC through the probe pads. The method further includes forming another layer of the IC over the second surface, and applying a second fault testing to the IC through the probe pads.

Abstract translation: 提供了一种用于测试单片堆叠集成电路（IC）的方法。 该方法包括接收IC层。 该层具有第一表面和第二表面，并且该层包括基底。 该方法还包括将探针焊盘附接到第一表面，以及通过探针焊盘对IC施加第一故障测试。 该方法还包括在第二表面上形成IC的另一层，并通过探针焊盘对IC施加第二故障测试。

公开(公告)号：US09222983B2

公开(公告)日：2015-12-29

申请号：US14027976

申请日：2013-09-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sandeep Kumar Goel

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: H01L22/20 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/3187 ,  H01L21/6835 ,  H01L21/822 ,  H01L22/32 ,  H01L2221/6835

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit and a scan segment in one of its layers. The test circuit includes a plurality of inputs, outputs, and multiplexers coupled to the scan segment and to a second layer of the IC. The test circuit further includes a plurality of control elements such that scan testing of the IC may be conducted on a layer-by-layer basis.

Abstract translation: 单片堆叠集成电路（IC）在其一个层中提供已知的良好层（KGL）测试电路和扫描段。 测试电路包括耦合到扫描段和IC的第二层的多个输入，输出和多路复用器。 测试电路还包括多个控制元件，使得IC的扫描测试可以逐层进行。

公开(公告)号：US20150077147A1

公开(公告)日：2015-03-19

申请号：US14030684

申请日：2013-09-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sandeep Kumar Goel

IPC: G01R31/28

CPC classification number: G01R31/318513 ,  G01R31/2882 ,  G01R31/31707 ,  G01R31/31718

Abstract: A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) path delay test circuit and at least a portion of a critical path in one of its layers. The test circuit includes a plurality of inputs, outputs, a flip-flop coupled to the at least a portion of the critical path and a multiplexer coupled to the flip-flop and to a second layer of the IC. The test circuit further includes a control element such that path delay testing of the IC may be conducted on a layer-by-layer basis.

Abstract translation: 单片堆叠集成电路（IC）具有已知的良好层（KGL）路径延迟测试电路和其一个层中的关键路径的至少一部分。 测试电路包括耦合到关键路径的至少一部分的多个输入，输出，触发器和耦合到触发器和多个IC的第二层的多路复用器。 测试电路还包括控制元件，使得IC的路径延迟测试可以在逐层的基础上进行。

公开(公告)号：US20140147972A1

公开(公告)日：2014-05-29

申请号：US14169799

申请日：2014-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mark Semmelmeyer ,  Sandeep Kumar Goel

IPC: H01L25/00

CPC classification number: H05K1/0201 ,  H01L21/561 ,  H01L22/22 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H05K1/11 ,  H05K1/144 ,  H05K3/46 ,  H05K2201/10734 ,  Y10T29/49124 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An embodiment is method comprising attaching a first die and a second die to a first surface of a first interposer using respective ones of first conductive connectors coupled to respective first surfaces of the first die and the second die; attaching a third die and a fourth die to a second surface of the first interposer using respective ones of second conductive connectors, the second surface of the first interposer being opposite the first surface of the interposer; and attaching the first die and the second die to a substrate using respective ones of third conductive connectors coupled to respective second surfaces of the first die and the second die.

Abstract translation: 实施例是一种方法，包括使用耦合到第一管芯和第二管芯的相应第一表面的相应的第一导电连接器将第一管芯和第二管芯附接到第一插入件的第一表面; 使用相应的第二导电连接器将第三管芯和第四管芯附接到第一插入件的第二表面，第一插入件的第二表面与插入件的第一表面相对; 以及使用耦合到所述第一管芯和所述第二管芯的相应第二表面的相应的第三导电连接器将所述第一管芯和所述第二管芯附接到衬底。

公开(公告)号：US12066490B2

公开(公告)日：2024-08-20

申请号：US17893236

申请日：2022-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Anshuman Chandra ,  Sandeep Kumar Goel

IPC: G01R31/3185 ,  G01R31/3187

CPC classification number: G01R31/318572 ,  G01R31/318536 ,  G01R31/318547 ,  G01R31/318555 ,  G01R31/3187

Abstract: Systems, methods, and devices are described herein for performing intra-die and inter-die tests of one or more dies of an integrated circuit. A cell of an integrated circuit includes a data register, an I/O pad, and a first multiplexer. The data register is configured to output a signal. The I/O pad is coupled to the data register and configured to receive and buffer the signal. The first multiplexer is coupled to the I/O pad and the data register. The multiplexer is configured to selectively output either the buffered signal or the signal based on whether a scan mode or a functional mode is enabled.

公开(公告)号：US20240087668A1

公开(公告)日：2024-03-14

申请号：US18512792

申请日：2023-11-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ankita Patidar ,  Sandeep Kumar Goel

IPC: G11C29/44 ,  G01R31/3183 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/50

CPC classification number: G11C29/44 ,  G01R31/318342 ,  G01R31/318547 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12005 ,  G11C29/50004 ,  G06F11/079

Abstract: A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.

公开(公告)号：US09835680B2

公开(公告)日：2017-12-05

申请号：US14659064

申请日：2015-03-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sandeep Kumar Goel ,  Yun-Han Lee ,  Saman M. I. Adham

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/3183

CPC classification number: G01R31/3008 ,  G01R31/318307

Abstract: A method performed at least partially by a processor includes performing a test sequence. In the test sequence, a test pattern is loaded into a circuit. The test pattern is configured to cause the circuit to output a predetermined test response. A test response is unloaded from the circuit after a test wait time period has passed since the loading of the test pattern into the circuit. The unloaded test response is compared with the predetermined test response.

公开(公告)号：US09651621B2

公开(公告)日：2017-05-16

申请号：US14328372

申请日：2014-07-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sandeep Kumar Goel

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3183

CPC classification number: G01R31/318342

Abstract: A method of detecting one or more faults in a semiconductor device that includes generating one or more secondary node lists from a primary node list. The primary node list includes one or more nodes. Each node of the one or more nodes of the primary node list is associated with a corresponding secondary node list of the one or more secondary node lists. The method also includes generating a test pattern set from the secondary node list and a fault list. The fault list identifies one or more faults.

公开(公告)号：US09633147B1

公开(公告)日：2017-04-25

申请号：US14874881

申请日：2015-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Stanley John ,  Sandeep Kumar Goel ,  Tze-Chiang Huang ,  Yun-Han Lee

IPC: G06F17/50

CPC classification number: G06F17/5022 ,  G06F17/5036 ,  G06F17/5045 ,  G06F2217/78

Abstract: In some embodiments, in a method performed by at least one processor for estimating an overall power state coverage of an electronic system level (ESL) model comprising a plurality of blocks for a module, a first value and a second value are set for each block of said plurality of blocks. At least one verification case is selected for each block in the ESL model. For each verification case of said at least one verification case: (a) a target coverage value is set, (b) a register transfer level (RTL) simulation is performed, (c) an actual coverage value is received, and (d) the first value or the second value is updated based on whether the actual coverage value is less than the target coverage value or not. A power state coverage is calculated for said each block. The overall power state coverage is calculated for the ESL model comprising said plurality of blocks for said module.

公开(公告)号：US09158881B2

公开(公告)日：2015-10-13

申请号：US14087650

申请日：2013-11-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sandeep Kumar Goel ,  Ashok Mehta

IPC: G06F17/50 ,  G01R31/28 ,  H01L21/66

CPC classification number: G06F17/5081 ,  G01R31/2818 ,  G01R31/2851 ,  G01R31/2853 ,  G01R31/318513 ,  G06F17/5077 ,  G06F2217/14 ,  G06F2217/40 ,  H01L22/00 ,  H01L22/14 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01014 ,  H01L2924/01047 ,  H01L2924/01011 ,  H01L2924/00012

Abstract: Provided is a method of assigning a first set of probe pads to an interposer for maximizing a defect coverage for the interposer. The interposer includes a second set of nets and the defect coverage is based on a ratio between a tested net length and an overall net length. The method includes processing the second set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two of the more than two micro-bumps are interconnected by one of the plurality of nets. The method further includes calculating an untested length of each net in the second set; selecting a first net from the second set with the maximum untested length; selecting two probe pads from the first set based on a user-defined cost function; and connecting the two probe pads to the first net with two dummy nets.

Abstract translation: 提供了一种将第一组探针焊盘分配给插入器以最大化插入器的缺陷覆盖的方法。 插入器包括第二组网络，并且缺陷覆盖范围基于被测净长度与总净长度之间的比率。 该方法包括处理第二组，使得互连多于两个微凸块的每个网络被分成多个网络，并且多于两个微凸块中的每两个通过多个网络中的一个互连。 该方法还包括计算第二组中每个网络的未测试长度; 从第二组中选择具有最大未测试长度的第一个网络; 基于用户定义的成本函数从第一组中选择两个探针焊盘; 并将两个探针焊盘连接到具有两个虚拟网络的第一个网络。