公开(公告)号：US10516026B2

公开(公告)日：2019-12-24

申请号：US16166603

申请日：2018-10-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.

公开(公告)号：US20190386061A1

公开(公告)日：2019-12-19

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US20190123264A1

公开(公告)日：2019-04-25

申请号：US16222031

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tong-Chern Ong ,  Wen-Ting Chu ,  Yu-Wen Liao ,  Kuei-Hung Shen ,  Kuo-Yuan Tu ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01L45/00 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1675

Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit includes a dielectric protection layer disposed over a dielectric structure that laterally surrounds one or more conductive interconnect layers. The dielectric protection layer has a protrusion extending outward from an upper surface of the dielectric protection layer. A bottom electrode is disposed over the dielectric protection layer and has sidewalls extending outward from a lower surface of the bottom electrode through the dielectric protection layer. The bottom electrode has a substantially planar upper surface over the protrusion. A data storage element is over the substantially planar upper surface of the bottom electrode, and a top electrode is over the data storage element.

公开(公告)号：US20190123184A1

公开(公告)日：2019-04-25

申请号：US16227931

申请日：2018-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Chi-Wen Liu ,  Ming Zhu

IPC: H01L29/66 ,  H01L29/739 ,  H01L21/324 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L29/06 ,  H01L29/786

Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

公开(公告)号：US10164076B2

公开(公告)日：2018-12-25

申请号：US15392579

申请日：2016-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Chi-Wen Liu ,  Ming Zhu

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/332 ,  H01L21/8238 ,  H01L29/739 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.

公开(公告)号：US20180166623A1

公开(公告)日：2018-06-14

申请号：US15894656

申请日：2018-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Carlos H. Diaz ,  Harry-Hak-Lay Chuang ,  Ru-Liang Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  H01L21/302

Abstract: A device includes a metal layer comprising a plurality of bottom electrode features. The device further includes a Magnetic Tunnel Junction (MTJ) stack layer comprising a plurality of MTJ stack features, each of the MTJ stack features disposed on a top surface of one of the plurality of bottom electrode features. The device further includes sidewall structures that extend along side surfaces of both the bottom electrode features and the MTJ stack features.

公开(公告)号：US20180097176A1

公开(公告)日：2018-04-05

申请号：US15809182

申请日：2017-11-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chern-Yow Hsu ,  Shih-Chang Liu

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/12

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ and is in direct electrical contact with a lower surface of the upper metal layer.

公开(公告)号：US09865610B2

公开(公告)日：2018-01-09

申请号：US15438907

申请日：2017-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Chin-Yi Huang ,  Shih-Chang Liu ,  Chang-Ming Wu

IPC: H01L27/11 ,  H01L27/115 ,  H01L27/11534 ,  H01L29/66 ,  H01L27/11521

CPC classification number: H01L27/11534 ,  H01L27/11521 ,  H01L29/66545

Abstract: The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.

公开(公告)号：US20170110559A1

公开(公告)日：2017-04-20

申请号：US15392579

申请日：2016-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Chi-Wen Liu ,  Ming Zhu

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/324 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/66977 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/7391 ,  H01L29/78618 ,  H01L29/78642

Abstract: A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.

公开(公告)号：US20170040429A1

公开(公告)日：2017-02-09

申请号：US15332115

申请日：2016-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/792 ,  H01L29/51 ,  H01L27/115

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42324 ,  H01L29/42348 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to a split gate memory device. In some embodiments, the split gate memory device includes a memory gate arranged over a substrate, and a select gate arranged over the substrate. An inter-gate dielectric layer is arranged between sidewalls of the memory gate and the select gate that face one another. The inter-gate dielectric layer extends under the memory gate. A first dielectric is disposed above the inter-gate dielectric layer and is arranged between the sidewalls of the memory gate and the select gate.

Abstract translation: 本公开涉及一种分离栅极存储器件。 在一些实施例中，分离栅极存储器件包括布置在衬底上的存储器栅极和布置在衬底上的选择栅极。 栅极间电介质层布置在存储器栅极的侧壁和彼此面对的选择栅极之间。 栅极间电介质层在存储栅下方延伸。 第一电介质设置在栅极间电介质层的上方，并且布置在存储栅极和选择栅极的侧壁之间。