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公开(公告)号：US10044390B2
公开(公告)日：2018-08-07
申请号：US15216615
申请日：2016-07-21
Applicant: QUALCOMM Incorporated
Inventor： Changhan Yun , Chengjie Zuo , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu , Jonghae Kim , David Berdy
IPC: H01L23/28 , H03H7/46 , H04B1/401 , H05K1/18 , H04B1/16 , H01L27/01 , H01L49/02 , H01L23/498 , H01L23/66 , H01L21/48
Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
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公开(公告)号：US20180145062A1
公开(公告)日：2018-05-24
申请号：US15861140
申请日：2018-01-03
Applicant: QUALCOMM Incorporated
Inventor： Je-Hsiung Jeffrey Lan , Niranjan Sunil Mudakatte , Changhan Hobie Yun , Daeik Daniel Kim , Chengjie Zuo , David Francis Berdy , Mario Francisco Velez , Jonghae Kim
IPC: H01L27/01 , H01L49/02 , H01L23/522 , H01L23/15
CPC classification number: H01L27/01 , H01G2/02 , H01G4/005 , H01L21/4846 , H01L23/15 , H01L23/49816 , H01L23/49822 , H01L23/5223 , H01L23/5227 , H01L28/10 , H01L28/75 , H01L2224/11
Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.
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53.发明授权公开(公告)号：US09966426B2
公开(公告)日：2018-05-08
申请号：US14853967
申请日：2015-09-14
Applicant: QUALCOMM Incorporated
Inventor： Niranjan Sunil Mudakatte , Daeik Daniel Kim , David Francis Berdy , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Chengjie Zuo , Mario Francisco Velez , Robert Paul Mikulka , Jonghae Kim
IPC: H01L23/057 , H01L23/48 , H01L23/495 , H01L49/02 , H01L23/522 , H01L27/08 , H01L23/00
CPC classification number: H01L28/60 , H01L23/5223 , H01L24/13 , H01L27/0805 , H01L28/87 , H01L28/91 , H01L2224/0401 , H01L2224/04042 , H01L2224/13109 , H01L2224/94 , H01L2924/10329 , H01L2924/1033 , H01L2924/10337 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2224/03
Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.
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公开(公告)号：US09935166B2
公开(公告)日：2018-04-03
申请号：US13833632
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
Inventor： Je-Hsiung Lan , Chengjie Zuo , Changhan Yun , David F. Berdy , Daeik D. Kim , Robert P. Mikulka , Mario Francisco Velez , Jonghae Kim
CPC classification number: H01L28/40 , G06F17/5068 , H01L23/15 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L27/016 , H01L27/12 , H01L28/10 , H01L28/60 , H01L2924/0002 , H01L2924/00
Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.
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公开(公告)号：US20180062617A1
公开(公告)日：2018-03-01
申请号：US15247803
申请日：2016-08-25
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie Yun , Je-Hsiung Lan , Chengjie Zuo , David Berdy , Jonghae Kim , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu
IPC: H03H9/205 , H01L41/332 , H03H9/54
CPC classification number: H03H9/205 , H01L41/332 , H03H3/04 , H03H9/173 , H03H9/54 , H03H2003/021 , H03H2003/0435 , H03H2003/0442 , H03H2003/0471
Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.
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Patent Agency Ranking
公开(公告)号：US09906318B2
公开(公告)日：2018-02-27
申请号：US14682023
申请日：2015-04-08
Applicant: QUALCOMM Incorporated
Inventor： Chengjie Zuo , Daeik Daniel Kim , David Francis Berdy , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Robert Paul Mikulka , Mario Francisco Velez , Jonghae Kim , Matthew Michael Nowak , Ryan Scott C. Spring , Xiangdong Zhang
CPC classification number: H04J1/08 , H03H7/465 , H03H2240/00 , H03H2250/00 , H04B1/0057 , H04B1/006 , H04B1/0064
Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.
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公开(公告)号：US20180026666A1
公开(公告)日：2018-01-25
申请号：US15216615
申请日：2016-07-21
Applicant: QUALCOMM Incorporated
Inventor： Changhan Yun , Chengjie Zuo , Mario Velez , Niranjan Sunil Mudakatte , Shiqun Gu , Jonghae Kim , David Berdy
CPC classification number: H04B1/1638 , H01F17/0013 , H01L21/4853 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/5223 , H01L23/64 , H01L23/66 , H01L24/19 , H01L24/20 , H01L27/01 , H01L28/10 , H01L28/40 , H01L2223/6616 , H01L2223/6672 , H01L2223/6677 , H01L2223/6688 , H01L2224/04105 , H01L2224/24195 , H01L2924/10253 , H01L2924/13091 , H01L2924/1421 , H01L2924/15153 , H01L2924/19041 , H01L2924/19042 , H01L2924/19105 , H04B1/006 , H05K1/165 , H05K1/185 , H05K3/4605 , H05K2201/09536 , H05K2201/097
Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.
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公开(公告)号：US20170331445A1
公开(公告)日：2017-11-16
申请号：US15151351
申请日：2016-05-10
Applicant: QUALCOMM Incorporated
Inventor： Yunfei Ma , Chengjie Zuo , David Francis Berdy , Daeik Daniel Kim , Changhan Hobie Yun , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Niranjan Sunil Mudakatte , Robert Paul Mikulka , Jonghae Kim
CPC classification number: H03H7/38 , H03H7/40 , H04B1/0458
Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.
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公开(公告)号：US09634640B2
公开(公告)日：2017-04-25
申请号：US13887568
申请日：2013-05-06
Applicant: QUALCOMM Incorporated
Inventor： Chengjie Zuo , Daeik D. Kim , Je-Hsiung Lan , Jonghae Kim , Mario Francisco Velez , Changhan Yun , David F. Berdy , Robert P. Mikulka , Matthew M. Nowak , Xiangdong Zhang , Puay H. See
IPC: H03H7/46
CPC classification number: H03H7/461 , H03H3/00 , H03H7/0115 , H03H7/463 , Y10T29/49016
Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.
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60.发明申请公开(公告)号：US20170062120A1
公开(公告)日：2017-03-02
申请号：US14841132
申请日：2015-08-31
Applicant: QUALCOMM Incorporated
Inventor： Changhan Hobie Yun , Mario Francisco Velez , Chengjie Zuo , Daeik Daniel Kim , David Francis Berdy , Je-Hsiung Jeffrey Lan , Jonghae Kim , Niranjan Sunil Mudakatte , Robert Paul Mikulka
IPC: H01F27/28 , H01F41/14 , H01F41/04 , H01F27/245
CPC classification number: H01F27/2804 , H01F17/0013 , H01F17/0033 , H01F27/245 , H01F41/042 , H01F41/046 , H01F41/14 , H01F41/32 , H01F2027/2809 , H01L23/645 , H01L2224/16225 , H01L2924/15311 , H01L2924/181 , H05K1/165 , H01L2924/00012
Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.
Abstract translation: 衬底包括第一介电层，至少部分地在第一介电层中的磁芯，其中磁芯包括第一非水平薄膜磁性（TFM）层。 衬底还包括包括多个第一互连件的第一电感器，其中第一电感器定位在衬底中以至少部分地围绕磁芯。 磁芯还可以包括第二非水平薄膜磁性（TFM）层。 磁芯还可以包括芯层。 磁芯还可以包括第三薄膜磁性（TFM）层和基本上平行于第三薄膜磁性（TFM）层的第四薄膜磁性（TFM）层。
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