公开(公告)号：US07993999B2

公开(公告)日：2011-08-09

申请号：US12614906

申请日：2009-11-09

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L21/8238

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

公开(公告)号：US20110115023A1

公开(公告)日：2011-05-19

申请号：US12621460

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/088 ,  H01L21/8238

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/785

摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.

摘要翻译： 公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。 沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。 三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。 三种不同类型的设备中的每一种具有单独优化的阈值。 还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。 该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

公开(公告)号：US20110111592A1

公开(公告)日：2011-05-12

申请号：US12614952

申请日：2009-11-09

申请人： KANGGUO CHENG ,  Bruce B. Doris ,  Ying Zhang

发明人： KANGGUO CHENG ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L21/306

CPC分类号： H01L21/28132 ,  H01L21/26586 ,  H01L29/66787

摘要： A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

摘要翻译： 一种用于制造集成电路的特征的方法及其装置包括在半导体器件的表面上形成第一结构并在第一结构的周围形成间隔物。 将角度离子注入施加到器件，使得间隔物具有来自成角度离子注入的保护部分和未受保护部分，其中未保护部分具有大于被保护部分的蚀刻速率的蚀刻速率。 相对于受保护部分，非保护部分和第一结构被选择性地去除。 将间隔物的受保护部分下面的层图案化以形成集成电路特征。

公开(公告)号：US20110042728A1

公开(公告)日：2011-02-24

申请号：US12542748

申请日：2009-08-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Charles William Koburger, III

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Charles William Koburger, III

IPC分类号： H01L29/78 ,  H01L21/31 ,  H01L21/318 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/8238

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76834 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

摘要翻译： 在一个实施例中，提供了一种用于在半导体器件中形成应力的方法。 半导体器件可以在衬底上包括栅极结构，其中栅极结构包括存在于栅极导体上的至少一个虚拟材料。 在半导体器件顶部形成保形电介质层，并且在保形电介质层上形成层间电介质层。 层间电介质层可以被平坦化以暴露在栅极结构顶部的保形电介质层的至少一部分，其中共形介电层的暴露部分可被去除以暴露栅极结构的上表面。 可以去除栅极结构的上表面以露出栅极导体。 然后可以在至少一个栅极导体上方形成应力诱导材料。

公开(公告)号：US07847356B2

公开(公告)日：2010-12-07

申请号：US12542855

申请日：2009-08-18

申请人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Tze-Chiang Chen ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L27/088 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/517

摘要： Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

摘要翻译： 公开了一种制造半导体器件的方法，以及根据该方法制造的器件。 该方法包括提供由硅构成的衬底; 执行浅沟槽隔离工艺以描绘nFET和pFET有源区域，并且在每个有源区域内，在衬底的表面上形成栅极结构，所述栅极结构从衬底的表面依次包括高介电常数 氧化物，由金属构成的层，由非晶硅构成的层以及由多晶硅构成的层。 提供由非晶硅组成的层，以至少在多晶硅层和/或金属层的沉积和加工过程中基本上防止高介电常数氧化物层在垂直方向上的再生长。

公开(公告)号：US20100203732A1

公开(公告)日：2010-08-12

申请号：US12368561

申请日：2009-02-10

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/302 ,  H01L21/30 ,  H01L21/308

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

摘要翻译： 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。

公开(公告)号：US07709902B2

公开(公告)日：2010-05-04

申请号：US12211647

申请日：2008-09-16

申请人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L31/119

CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

摘要翻译： 提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。 根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质 堆没有净正电荷。 特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。 在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质 。

公开(公告)号：US07691482B2

公开(公告)日：2010-04-06

申请号：US11473835

申请日：2006-06-23

申请人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Philip J. Oldiges ,  Min Yang

发明人： Huilong Zhu ,  Bruce B. Doris ,  Meikei Ieong ,  Philip J. Oldiges ,  Min Yang

IPC分类号： B32B9/04 ,  H01L27/12

CPC分类号： H01L21/76254 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/84 ,  H01L29/045 ,  H01L29/785 ,  Y10T428/249921 ,  Y10T428/249922

摘要： The present invention provides a method of forming a substantially planar SOI substrate having multiple crystallographic orientations including the steps of providing a multiple orientation surface atop a single orientation layer, the multiple orientation surface comprising a first device region contacting and having a same crystal orientation as the single orientation layer, and a second device region separated from the first device region and the single orientation layer by an insulating material, wherein the first device region and the second device region have different crystal orientations; producing a damaged interface in the single orientation layer; bonding a wafer to the multiple orientation surface; separating the single orientation layer at the damaged interface; wherein a damaged surface of said single orientation layer remains; and planarizing the damaged surface until a surface of the first device region is substantially coplanar to a surface of the second device region.

摘要翻译： 本发明提供一种形成具有多个结晶取向的基本上平面的SOI衬底的方法，包括以下步骤：在单个取向层的顶部提供多个取向表面，所述多个取向表面包括与第一器件区域接触并具有与 单取向层和通过绝缘材料与第一器件区域和单取向层分离的第二器件区域，其中第一器件区域和第二器件区域具有不同的晶体取向; 在单取向层产生损坏的界面; 将晶片接合到所述多个取向表面; 在损坏的界面处分离单个取向层; 其中所述单取向层的损伤表面保留; 以及平坦化损坏的表面，直到第一器件区域的表面基本上与第二器件区域的表面共面。

公开(公告)号：US20100048027A1

公开(公告)日：2010-02-25

申请号：US12195691

申请日：2008-08-21

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/30608 ,  H01L29/045 ,  H01L29/66795

摘要： A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.

摘要翻译： 公开了一种半导体鳍片结构的处理方法。 该方法包括在含有氢同位素的环境中对翅片结构进行热退火。 在热退火步骤之后，鳍结构被蚀刻成晶体取向的自限制的方式。 取决于晶体取向的蚀刻可以选择为含有氢氧化铵（NH 4 OH）的水溶液。 完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。 翅片结构侧壁是{110}平面。

公开(公告)号：US20100038705A1

公开(公告)日：2010-02-18

申请号：US12190109

申请日：2008-08-12

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Haining S. Yang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28026 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method.

摘要翻译： 半导体结构和用于制造半导体结构的方法在诸如场效应晶体管结构的场效应结构内的与栅电极相邻的间隔物之下提供底切。 可以完全或不完全地覆盖插入在间隔物和半导体衬底之间的区域的底切部被栅极电介质填充。 与栅极和半导体衬底相比，栅极电介质具有比间隔物和半导体衬底之间更大的厚度。 可以使用顺序替换栅极电介质和栅极电极法制造半导体结构。