公开(公告)号：US20160357044A1

公开(公告)日：2016-12-08

申请号：US14891729

申请日：2015-05-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhijun Lv ,  Tailiang Li ,  Tao Gao ,  Ce Ning ,  Shuang Sun

IPC: G02F1/1368 ,  G02F1/1343 ,  H01L29/417 ,  H01L29/45 ,  H01L29/423 ,  G02F1/1335 ,  H01L29/49

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/133553 ,  G02F1/13439 ,  G02F1/1362 ,  G02F1/136227 ,  G02F2201/123 ,  G02F2203/02 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908

Abstract: The present disclosure discloses an array substrate, comprising a substrate, a plurality of pixel regions on the substrate, and a thin-film transistor formed in each of the pixel regions, each of the pixel regions comprising a pixel electrode region, wherein, the thin-film transistor comprises a gate layer and a source/drain layer formed laminatedly on the substrate; the array substrate further comprises a flat layer and a reflective metal layer formed in sequence on the substrate and covering at least the pixel electrode region and the thin-film transistor; the reflective metal layer is electrically connected to a drain of the thin-film transistor; and at least one of the gate layer and the source/drain layer is formed of a single metal layer. The present disclosure further provides a method for manufacturing the array substrate and a totally reflective type liquid crystal display comprising the array substrate.

Abstract translation: 本公开公开了一种阵列基板，包括基板，基板上的多个像素区域和形成在每个像素区域中的薄膜晶体管，每个像素区域包括像素电极区域，其中，薄的 薄膜晶体管包括层叠在基板上的栅极层和源极/漏极层; 阵列基板还包括依次形成在基板上并覆盖至少像素电极区域和薄膜晶体管的平坦层和反射金属层; 反射金属层电连接到薄膜晶体管的漏极; 并且栅极层和源极/漏极层中的至少一个由单个金属层形成。 本公开还提供了一种用于制造阵列基板的方法和包括阵列基板的全反射型液晶显示器。

公开(公告)号：US09373649B2

公开(公告)日：2016-06-21

申请号：US14422342

申请日：2014-06-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Ce Ning ,  Wei Yang ,  Ke Wang

IPC: H01L29/10 ,  H01L27/12 ,  G02F1/1343

CPC classification number: H01L27/1248 ,  G02F2001/134372 ,  H01L27/1259 ,  H01L27/1288

Abstract: The invention belongs to the field of display technology, and particularly provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and a thin film transistor and driving electrodes provided on the base substrate, the thin film transistor includes a gate, a gate insulating layer, an active layer, a source and a drain, the driving electrodes include a slit-shaped electrode and a plate-shaped electrode which are located in different layers and at least partially overlap with each other in the orthographic projection direction, the source, the drain and the active layer are formed so that part of their bottom surfaces are located in the same plane, and a resin layer is further provided between the thin film transistor and the plate-shaped electrode.

Abstract translation: 本发明属于显示技术领域，特别是提供阵列基板及其制造方法以及显示装置。 阵列基板包括基底基板和设置在基底基板上的薄膜晶体管和驱动电极，薄膜晶体管包括栅极，栅极绝缘层，有源层，源极和漏极，驱动电极包括 狭缝状电极和板状电极，其位于不同的层中并且在正投影方向上彼此至少部分重叠，源极，漏极和有源层形成为使得它们的底表面的一部分位于 在同一平面内，在薄膜晶体管和板状电极之间进一步设置树脂层。

公开(公告)号：US12235557B2

公开(公告)日：2025-02-25

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US12230683B2

公开(公告)日：2025-02-18

申请号：US17755380

申请日：2021-05-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Hehe Hu ,  Tianmin Zhou ,  Jipeng Song

IPC: H01L29/786 ,  H01L29/417

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

公开(公告)号：US12183409B2

公开(公告)日：2024-12-31

申请号：US17909129

申请日：2021-10-25

Applicant: BOE Technology Group Co., Ltd.

Inventor： Fengjuan Liu ,  Ce Ning ,  Wei Liu ,  Dini Xie ,  Yuhang Lu

IPC: G11C19/28 ,  G09G3/20

Abstract: Provided is a shift register unit. The shift register unit includes an input circuit, a compensation control circuit, and an output circuit; wherein input circuit coupled to an input signal terminal, an input control terminal, a first power supply terminal, a reference node, and a first node; the compensation control circuit coupled to a first clock signal terminal, the reference node, and the first node; and the output circuit coupled to the first node, a second clock signal terminal, and an output terminal.

公开(公告)号：US12068355B2

公开(公告)日：2024-08-20

申请号：US17410677

申请日：2021-08-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu He ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Jie Huang ,  Nianqi Yao ,  Kun Zhao

IPC: H01L27/146 ,  H01L27/12

CPC classification number: H01L27/14643 ,  H01L27/1214 ,  H01L27/14689

Abstract: An array substrate includes a substrate, the array substrate includes a display region and a detection region. And the detection region includes a thin film transistor located on the substrate and a photodiode located on one side of the thin film transistor away from the substrate, and the array substrate further includes a first inorganic protective layer, an organic protective layer and a second inorganic protective layer located between the thin film transistor and the photodiode. And the first inorganic protective layer, the organic protective layer and the second inorganic protective layer are stacked in sequence in a direction away from the substrate, and an orthographic projection of the photodiode on the substrate is within the range of the orthographic projection of the organic protective layer on the substrate.

公开(公告)号：US20240272497A1

公开(公告)日：2024-08-15

申请号：US18005421

申请日：2022-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Binbin Tong ,  Lizhong Wang ,  Jianbo Xian ,  Liping Lei ,  Chunping Long ,  Yunping Di ,  Ce Ning

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/133308 ,  G02F1/13439

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.

公开(公告)号：US20240212564A1

公开(公告)日：2024-06-27

申请号：US17913258

申请日：2021-11-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Binbin Tong ,  Chengfu Xu ,  Dapeng Xue ,  Shuilang Dong ,  Nianqi Yao

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/062 ,  G09G2310/08

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are provided. In the present disclosure, a first transistor group with oxide semiconductor as an active layer material is disposed on a side of a second transistor group with polysilicon as an active layer material away from the base, and an area enclosed by orthographic projections of the transistors in the first transistor group on the base is overlapped with an area enclosed by orthographic projections of the transistors in the second transistor group on the base. Stable performance of the transistors included can be ensured in a manufacturing process of the first transistor group and the second transistor group located in different layers, and at the same time, an area occupied by the driving circuit can be reduced so as to decrease a frame width of a display apparatus or improve resolution of the display apparatus.

公开(公告)号：US20230329037A1

公开(公告)日：2023-10-12

申请号：US18022924

申请日：2022-03-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Meng Zhao ,  Feng Guan ,  Wei Liu ,  Fengjuan Liu ,  Lubin Shi ,  Ce Ning

IPC: H10K59/121 ,  H10K59/131 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H10K59/131 ,  H10K59/1201 ,  H10K59/1216

Abstract: A display base plate, a preparation method therefor and a display panel are provided in the present disclosure. The display panel can greatly improve resolution while ensuring low power consumption. The display base plate includes a plurality of sub-pixels. Each of the plurality of sub-pixels includes a storage capacitor, a polysilicon transistor and at least one oxide transistor. The storage capacitor includes a first electrode and a second electrode oppositely arranged, and first electrode is arranged at a side of the second electrode away from the substrate. The second electrode is arranged in the same layer as a gate electrode of the polysilicon transistor. The at least one oxide transistor is arranged on a side of the first electrode away from the substrate, and the first electrode at least partially overlaps with an active layer of the at least one oxide transistor in a direction perpendicular to the substrate.

公开(公告)号：US11648558B2

公开(公告)日：2023-05-16

申请号：US16605776

申请日：2019-05-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiaochen Ma ,  Guangcai Yuan ,  Ce Ning ,  Xin Gu ,  Hehe Hu

IPC: B01L3/00 ,  G01N27/12 ,  G01N33/487

CPC classification number: B01L3/502761 ,  B01L3/502707 ,  G01N27/128 ,  B01L2200/0647 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0864 ,  B01L2300/0887 ,  B01L2300/12 ,  B01L2400/0421 ,  G01N33/48721

Abstract: A biosensor apparatus is provided. The biosensor apparatus includes a base substrate; a first fluid channel layer on the base substrate and having a first fluid channel passing therethrough; a foundation layer on a side of the first fluid channel layer away from the base substrate, a foundation layer throughhole extending through the foundation layer to connect to the first fluid channel; and a micropore layer on a side of the foundation layer away from the base substrate, a micropore extending through the micropore layer to connect to the first fluid channel through the foundation layer throughhole. The micropore layer extends into the foundation layer throughhole and at least partially covers an inner wall of the foundation layer throughhole.