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    Data processing device
    51.
    发明申请
    Data processing device 有权

    公开(公告)号：US20060114737A1

    公开(公告)日：2006-06-01

    申请号：US11138344

    申请日：2005-05-27

    Applicant: Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

    Inventor： Masaaki Terasawa ,  Yoshiki Kawajiri ,  Takanori Yamazoe

    IPC: G11C5/14

    CPC classification number: G11C16/0466 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

    Abstract: A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having drain electrodes and source electrodes respectively coupled to bit lines and source lines and gate electrodes coupled to word lines and storing information based on a difference between threshold voltages to a word line select level in read operation, and the nonvolatile memory has a low power consumption mode. In the low power consumption mode, a second voltage lower than a circuit ground voltage and higher than a first negative voltage necessary for read operation is supplied to the well regions and word lines. When boost forming a rewriting negative voltage therein, a circuit node at a negative voltage is not the circuit ground voltage in the low power consumption mode.

    Data processing apparatus
    52.
    发明申请
    Data processing apparatus 有权
    数据处理装置

    公开(公告)号：US20050237825A1

    公开(公告)日：2005-10-27

    申请号：US11115132

    申请日：2005-04-27

    Applicant: Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

    Inventor： Yoshiki Kawajiri ,  Masaaki Terasawa ,  Takanori Yamazoe

    IPC: H01L27/04 ,  G11C5/14 ,  G11C7/00 ,  G11C16/12 ,  H01L21/822 ,  H03K5/08

    CPC classification number: G11C5/145 ,  G11C16/12

    Abstract: The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about ⅓ of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.

    Abstract translation: 本发明旨在大大降低为EEPROM提供的升压电路的操作时的峰值电流。 在擦除/写入操作中，首先，作为选择时钟信号的低频时钟信号通过低频时钟控制信号输入到电荷泵。 在经过一定时间（大约下降时间的1/3）之后，通过高频时钟控制信号输出频率高于低频时钟信号的高频时钟信号，作为 选择时钟信号到电荷泵以将电压升高到预定的电压电平。 以这种方式，在抑制消耗电流的峰值的同时，可以缩短升压电压的下降时间。

    Nonvolatile memory and semiconductor device with controlled voltage booster circuit
    54.
    发明授权
    Nonvolatile memory and semiconductor device with controlled voltage booster circuit 有权
    具有受控升压电路的非易失性存储器和半导体器件

    公开(公告)号：US06542411B2

    公开(公告)日：2003-04-01

    申请号：US09970675

    申请日：2001-10-05

    Applicant: Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

    Inventor： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Yoshiki Kawajiri ,  Masamichi Fujito

    IPC: G11C1604

    CPC classification number: G11C16/3472 ,  G11C16/30 ,  G11C16/3468 ,  G11C16/3481

    Abstract: A nonvolatile memory includes a control register (CRG) for providing instructions as to basic operations such as writing, erasing, reading, etc., a boosted voltage attainment detecting circuit for detecting whether a voltage boosted by a booster circuit has reached a desired level, a circuit which counts the time required to apply each of write and erase voltages, and a circuit which detects the completion of the writing or erasing. Respective operations are automatically advanced by simple setting of the operation instructions to the control register. After the completion of the operations, an end flag (FLAG) provided within the control register is set to notify the completion of the writing or erasing.

    Abstract translation: 非易失性存储器包括用于提供关于基本操作（诸如写入，擦除，读取等）的指令的控制寄存器（CRG），用于检测由升压电路升压的电压是否达到期望水平的升压电压达到检测电路， 计算施加写入和擦除电压中的每一个所需的时间的电路，以及检测写入或擦除完成的电路。 通过将操作指令简单设置到控制寄存器，可以自动提高各自的操作。 操作完成后，设置控制寄存器内提供的结束标志（FLAG），通知写入或擦除完成。

    Large scale integrated circuit for low voltage operation
    56.
    发明授权
    Large scale integrated circuit for low voltage operation 失效
    用于低压运行的大规模集成电路

    公开(公告)号：US5297097A

    公开(公告)日：1994-03-22

    申请号：US366869

    申请日：1989-06-14

    Applicant: Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    Inventor： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

    IPC: G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/407

    CPC classification number: G11C11/4096 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/147

    Abstract: Disclosed is a one-chip ULSI which can carry out fixed operations for a wide range of power supply voltages (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which provides a fixed internal voltage for a wide range of power supply voltages, an input/output buffer which can be adapted to several input/out interface levels, a dynamic or volatile RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

    Abstract translation: 公开了一种单芯片ULSI，其可以对宽范围的电源电压（1V至5.5V）进行固定操作。 该单芯片ULSI由一个电压转换器电路组成，该电路为广泛的电源电压提供固定的内部电压，可适应多个输入/输出接口电平的输入/输出缓冲器，动态或 可以在2V以下的电源电压下工作的易失性RAM。该单芯片ULSI可以应用于紧凑型便携式电子设备，例如笔记本型个人计算机，电子口袋笔记本 ，固态摄像机等

    Semiconductor integrated circuit device
    57.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5289425A

    公开(公告)日：1994-02-22

    申请号：US870460

    申请日：1992-04-17

    Applicant: Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

    Inventor： Masashi Horiguchi ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Goro Kitsukawa ,  Takayuki Kawahara ,  Takesada Akiba

    IPC: G01R31/317 ,  G05F3/24 ,  G11C5/14 ,  G11C8/00

    CPC classification number: G11C5/147 ,  G01R31/31715 ,  G05F3/24

    Abstract: An intermediate voltage generating circuit for generating a voltage lying between an external power supply voltage and a ground voltage, and two voltage limiter circuits for generating internal power supply voltages and stabilized with this intermediate voltage as a reference are provided in a semiconductor integrated circuit. Even if the external power supply voltage or the ground voltage fluctuates, no disagreement is produced between a logical threshold of a circuit operating on the external power supply voltage and a logical threshold of a circuit operating on the internal power supply voltage.

    Abstract translation: 在半导体集成电路中设置有用于产生位于外部电源电压和接地电压之间的电压的中间电压产生电路和用于产生内部电源电压并以该中间电压稳定的两个限压器电路。 即使外部电源电压或接地电压发生波动，也不会在外部电源电压工作的电路的逻辑阈值与内部电源电压的电路的逻辑阈值之间产生不同意见。

    Driver circuit having a current mirror circuit
    59.
    发明授权
    Driver circuit having a current mirror circuit 失效
    具有电流镜电路的驱动电路

    公开(公告)号：US4873673A

    公开(公告)日：1989-10-10

    申请号：US126485

    申请日：1987-11-30

    Applicant: Ryoichi Hori ,  Kiyoo Itoh ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takao Watanabe ,  Takayuki Kawahara

    Inventor： Ryoichi Hori ,  Kiyoo Itoh ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Takao Watanabe ,  Takayuki Kawahara

    IPC: G11C11/4094

    CPC classification number: G11C11/4094

    Abstract: A semiconductor device is provided wherein a current mirror circuit controlled by a pulse input voltage is utilized and a load is driven in such a manner that the output current of the current mirror circuit becomes a substantially constant current. Further, the output voltage of the current mirror circuit can be compared with a predetermined reference voltage by a comparator, with the current mirror circuit being controlled by the output voltage of the comparator in accordance with the result of comparison. The driver circuit can be used for driving the data lines of a dynamic random access memory or an external capacitance load. With these techniques, power consumption and peak current are reduced.

    Abstract translation: 提供一种半导体器件，其中利用由脉冲输入电压控制的电流镜像电路，并且以使得电流镜像电路的输出电流变为基本上恒定的电流的方式驱动负载。 此外，可以通过比较器将电流镜电路的输出电压与预定的参考电压进行比较，根据比较结果，电流镜电路由比较器的输出电压控制。 驱动电路可用于驱动动态随机存取存储器的数据线或外部电容负载。 利用这些技术，功耗和峰值电流降低。

    Nonvolatile semiconductor memory using an adjustable threshold voltage transistor in a flip-flop
    60.
    发明授权
    Nonvolatile semiconductor memory using an adjustable threshold voltage transistor in a flip-flop 有权
    非挥发性半导体存储器在触发器中使用可调阈值电压晶体管

    公开(公告)号：US07969780B2

    公开(公告)日：2011-06-28

    申请号：US11776491

    申请日：2007-07-11

    Applicant: Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

    Inventor： Taku Ogura ,  Masaaki Mihara ,  Yoshiki Kawajiri

    IPC: G11C11/34 ,  G11C14/00

    CPC classification number: G11C11/412 ,  G11C14/00 ,  G11C14/0063

    Abstract: An object of this invention is to provide a rewritable nonvolatile memory cell that can have a wide reading margin, and can control both a word line and a bit line by changing the level of Vcc. As a solution, a flip-flop is formed by cross (loop) connect of inverters including memory transistors that can control a threshold voltage by charge injection into the side spacer of the transistors. In the case of writing data to one memory transistor, a high voltage is supplied to a source of the memory transistor through a source line and a high voltage is supplied to a gate of the memory transistor through a load transistor of the other side inverter. In the case of erasing the written data, a high voltage is supplied to the source of the memory transistor through the source line.

    Abstract translation: 本发明的目的是提供一种可以具有宽的读取余量的可重写非易失性存储单元，并且可以通过改变Vcc的电平来控制字线和位线。 作为解决方案，触发器是通过包括存储晶体管的逆变器的交叉（环路）连接形成的，所述存储器晶体管可以通过电荷注入到晶体管的侧面间隔来控制阈值电压。 在向一个存储晶体管写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极，并且通过另一侧反相器的负载晶体管将高电压提供给存储晶体管的栅极。 在擦除写入数据的情况下，通过源极线将高电压提供给存储晶体管的源极。

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