公开(公告)号：US20090130791A1

公开(公告)日：2009-05-21

申请号：US12274642

申请日：2008-11-20

Applicant: Woon-Seong KWON ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

Inventor： Woon-Seong KWON ,  Tae-Je CHO ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC: H01L21/00

CPC classification number: H04N5/2252 ,  H01L27/14618 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/00014 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: Provided are camera modules capable of effectively shielding electromagnetic (EM) waves and methods of fabricating the same. A method of fabricating a camera module includes, preparing a first wafer including an array of lens units. Then, a second wafer including an array of image sensor CSPs (chip-scale packages) is prepared. Each of the image sensor CSPs includes an image sensor chip corresponding to one of the lens units. The first wafer is stacked on the second wafer. The first wafer and the second wafer are cut to form a trench exposing the top surface of the image sensor chip at the interface between adjacent lens units. The trench is filled with a first material used for forming a housing. The first material and the image sensor chip are cut at the interface between the adjacent lens units.

Abstract translation: 提供能够有效屏蔽电磁波（EM）波的相机模块及其制造方法。 制造相机模块的方法包括：制备包括透镜单元阵列的第一晶片。 然后，制备包括图像传感器CSP阵列（芯片级封装）的第二晶片。 图像传感器CSP中的每一个包括对应于一个透镜单元的图像传感器芯片。 第一晶片被堆叠在第二晶片上。 切割第一晶片和第二晶片以形成在相邻透镜单元之间的界面处暴露图像传感器芯片的顶表面的沟槽。 沟槽填充有用于形成壳体的第一材料。 第一材料和图像传感器芯片在相邻透镜单元之间的界面处被切割。

公开(公告)号：US20080258299A1

公开(公告)日：2008-10-23

申请号：US12073310

申请日：2008-03-04

Applicant: Un Byoung Kang ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

Inventor： Un Byoung Kang ,  Yong Hwan Kwon ,  Chung Sun Lee ,  Woon Seong Kwon ,  Hyung Sun Jang

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/83 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13099 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/01007 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成扩散阻挡层，并在衬底上形成至少两个特征，使得扩散阻挡层分别设置在每个特征和衬底之间，并接触至少两个特征。 衬底的第一杂质区包含第一类杂质，衬底的第二杂质区包含不同于第一类型的第二类杂质，所述至少两个特征的第一特征在第一杂质区， 并且所述至少两个特征的第二特征在于第二杂质区域，使得第二特征通过不同的杂质区域与第一特征电隔离。

公开(公告)号：US20080251872A1

公开(公告)日：2008-10-16

申请号：US11831768

申请日：2007-07-31

Applicant: Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

Inventor： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC: H01L27/12 ,  H01L21/02

CPC classification number: H01L27/14618 ,  H01L24/97 ,  H01L27/14625 ,  H01L27/14683 ,  H01L27/14685 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An image sensor package, a method of manufacturing the same, and an image sensor module including the image sensor package are provided. In the image sensor package, an image sensor chip is installed onto a depression of a transmissive substrate. An adhesive bonds the image sensor chip to the transmissive substrate and seals an Active Pixel Sensor (APS) on the image sensor chip, protecting it from fine particle contamination. An IR cutting film is disposed on the transmissive substrate to minimize the height of the image sensor package. The image sensor package is electrically connected to external connection pads in the depression. Consequently, the image sensor package has a minimum height, is not susceptible to particle contamination, and does not require expensive alignment processes during manufacturing.

Abstract translation: 提供了图像传感器封装，其制造方法和包括图像传感器封装的图像传感器模块。 在图像传感器封装中，将图像传感器芯片安装在透光性基板的凹部上。 粘合剂将图像传感器芯片粘合到透射基板上，并将图像传感器芯片上的有源像素传感器（APS）密封并保护其免受细颗粒污染。 将IR切割膜设置在透射基底上以最小化图像传感器封装的高度。 图像传感器封装电连接到凹陷中的外部连接焊盘。 因此，图像传感器封装具有最小高度，不易受到颗粒污染，并且在制造期间不需要昂贵的对准过程。

公开(公告)号：US20080012084A1

公开(公告)日：2008-01-17

申请号：US11826124

申请日：2007-07-12

Applicant: Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

Inventor： Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC: H01L31/0232

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An image sensor package may include a transparent substrate, an image sensor chip having a sensing region disposed over the transparent substrate, a resin protection dam disposed between the image sensor chip and the transparent substrate inside a wiring pattern, the resin protection dam having an aperture formed to expose a sensing region of the image sensor chip and defining a cavity between the sensing region and the transparent substrate, a resin filled on the transparent substrate outside the resin protection dam, and a black matrix pattern disposed on each side of the transparent substrate and configured to block excess transmission of light.

Abstract translation: 图像传感器封装可以包括透明基板，具有设置在透明基板上的感测区域的图像传感器芯片，设置在图像传感器芯片和布线图案内的透明基板之间的树脂保护坝，树脂保护坝具有孔 形成为暴露图像传感器芯片的感测区域并且在感测区域和透明基板之间限定空腔，填充在树脂保护堤外的透明基板上的树脂和布置在透明基板的每一侧上的黑矩阵图案 并且被配置为阻止光的过量透射。

公开(公告)号：US20060157826A1

公开(公告)日：2006-07-20

申请号：US11247307

申请日：2005-10-12

Applicant: Hee-seok Lee ,  Un-byoung Kang ,  Yun-hyeok Im

Inventor： Hee-seok Lee ,  Un-byoung Kang ,  Yun-hyeok Im

IPC: H01L23/58

CPC classification number: H05K3/4641 ,  H01L23/66 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/09 ,  H05K2201/0338 ,  H05K2201/0352 ,  H01L2924/00

Abstract: A multi-path printed circuit board (PCB) comprising separate direct current (DC) and alternating current (AC) paths, and a power delivery system including the same are provided. The multi-path PCB comprises a plurality of planar layers, each comprising a metal layer, and a plurality of insulators interposed between the planar layers. The metal layers may have different conductivities. The power delivery system includes a power source, a semiconductor IC, and the multi-path PCB. The multi-path PCB is adapted to function as a power delivery path for delivering power from the power source to the semiconductor IC.

Abstract translation: 提供了包括单独的直流（DC）和交流（AC）路径的多路径印刷电路板（PCB），以及包括其的电力输送系统。 多路径PCB包括多个平面层，每个平面层包括金属层，以及介于平面层之间的多个绝缘体。 金属层可以具有不同的电导率。 电力输送系统包括电源，半导体IC和多路PCB。 多路径PCB适于用作将功率从电源传送到半导体IC的功率传递路径。

公开(公告)号：US20060094848A1

公开(公告)日：2006-05-04

申请号：US11311198

申请日：2005-12-19

Applicant: Byoung Kang ,  Hyuk Moon ,  Jong Lee ,  Kyoung Wi ,  Tae Kim

Inventor： Byoung Kang ,  Hyuk Moon ,  Jong Lee ,  Kyoung Wi ,  Tae Kim

IPC: C08G77/04 ,  C08G77/46

CPC classification number: C08G59/306 ,  C08G59/3254 ,  C08G59/504 ,  C08L61/00 ,  C08L79/08 ,  C08L83/00 ,  C09J5/02 ,  C09J2400/123 ,  C09J2400/143 ,  C09J2400/163 ,  C09J2461/00 ,  C09J2479/00 ,  C09J2483/00 ,  H05K3/389

Abstract: The present invention relates to silane adducts having a relatively higher adhesive strength as expressed formula X3SiR1, and manufacturing method thereof. wherein X is a hydrogenated form selected from one of epoxy compounds, amino compounds and bisphenolic, and R1 is selected from one of glycidyloxypropyl group, 2-(3,4-epoxycyclohexyl)ethyl group, 3-acryloxypropyl group, 3-methacryloxypropyl group, amino-propyl group, 3-[2-(2-aminoethylamino)ethylamino]propyl group, N-methylaminopropyl group, N-phenylaminopropyl group, N,N-dimethyl-3-aminopropyl group, mercapto-propyl group, cyano-propyl group, and isocyanato-propyl group.

公开(公告)号：US20060091504A1

公开(公告)日：2006-05-04

申请号：US11256650

申请日：2005-10-21

Applicant: Un-Byoung Kang ,  Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon

Inventor： Un-Byoung Kang ,  Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon

IPC: H01L23/58

CPC classification number: H05K3/3463 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13144 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/8181 ,  H01L2224/81825 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/189 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: In one embodiment, a film circuit substrate comprises an insulating film made of polyimide resin; a conductive circuit pattern formed on the insulating film, the circuit pattern including an inner lead to be connected with a conductive bump of a semiconductor chip through a bump bonding process; and a tin-indium alloy layer formed on the inner lead to produce an inter-metallic compound layer of AuxSn composition during the bump bonding process.

Abstract translation: 在一个实施例中，薄膜电路基板包括由聚酰亚胺树脂制成的绝缘膜; 形成在所述绝缘膜上的导电电路图案，所述电路图案包括通过凸块接合工艺与半导体芯片的导电凸块连接的内部引线; 以及形成在内部引线上的锡铟合金层，以在凸点焊接工艺期间产生Au / Sn组分的金属间化合物层。

公开(公告)号：US20050104370A1

公开(公告)日：2005-05-19

申请号：US10788366

申请日：2004-03-01

Applicant: Hyung Kim ,  In Jeon ,  Sung Hur ,  Chun Chol ,  Byoung Kang

Inventor： Hyung Kim ,  In Jeon ,  Sung Hur ,  Chun Chol ,  Byoung Kang

IPC: F16L41/00 ,  F16L47/32 ,  F16L39/00

CPC classification number: F16L47/32

Abstract: A hose clamping assembly comprises a branched pipe having a plurality of projected stoppers thereon, each of the stoppers formed around an outer surface of each branch of the branched pipe and spaced apart a certain distance from each other, a hose connected to each branch of the branched pipe by sliding onto each of the branches, the hose contacting a nearest stopper from the end portion of the branch among the plurality of stoppers, a clamp formed on an outer surface of the hose and between the stoppers by a molding apparatus, a portion of the clamp on the outer surface of the hose connected to a portion of the clamp between the stoppers and an arm connecting the clamp to an adjacent clamp having a different axial direction, the arm formed by the molding apparatus.

Abstract translation: 软管夹紧组件包括分支管，其上具有多个突出的塞子，每个止动件形成在分支管的每个分支的外表面周围并彼此隔开一定距离，连接到 分支管通过滑动到每个分支上，软管接触来自多个止动件中的分支端部的最近的止动件，夹具形成在软管的外表面上，并通过模制装置形成在止动件之间，部分 所述夹具的外表面上的连接到所述夹持件的所述止动件的一部分之间的所述夹具，以及将所述夹具连接到具有不同轴向方向的相邻夹具的臂，所述臂由所述模制设备形成。

公开(公告)号：US09941196B2

公开(公告)日：2018-04-10

申请号：US15130904

申请日：2016-04-15

Applicant: Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

Inventor： Ho-Jin Lee ,  Tae-Je Cho ,  Dong-Hyeon Jang ,  Ho-Geon Song ,  Se-Young Jeong ,  Un-Byoung Kang ,  Min-Seung Yoon

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/525

CPC classification number: H01L23/49844 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/525 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/15311

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

公开(公告)号：US20170004990A1

公开(公告)日：2017-01-05

申请号：US15112429

申请日：2014-03-19

Applicant: Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

Inventor： Un-Byoung Kang ,  Joonsik Sohn ,  Jung-Seok Ahn ,  Chungsun Lee ,  Taeje Cho

IPC: H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L21/6836 ,  H01L21/48 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/544 ,  H01L24/02 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2223/5446 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/11 ,  H01L21/304 ,  H01L2221/68363 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/03 ,  H01L2224/85

Abstract: Provided are methods of fabricating a semiconductor device. According to the method, a first glue layer, a first release layer, a second glue layer, and a second release layer may be sequentially interposed between a carrier and a device wafer. All of the first glue layer, the first release layer, the second glue layer, and the second release layer may be formed of thermosetting resin.

Abstract translation: 提供制造半导体器件的方法。 根据该方法，第一胶合层，第一剥离层，第二胶层和第二剥离层可以顺序插入载体和器件晶片之间。 所有第一胶合层，第一释放层，第二胶层和第二剥离层可以由热固性树脂形成。