公开(公告)号：US20090175078A1

公开(公告)日：2009-07-09

申请号：US12365648

申请日：2009-02-04

Applicant: Gerrit Jan Hemink

Inventor： Gerrit Jan Hemink

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.

Abstract translation: 在编程操作期间，未编程（或禁止）非易失性存储元件意图编程另一非易失性存储元件的无意编程被称为“程序干扰”。 提出了一种用于编程和/或读取非易失性存储器的系统，其减少了编程干扰的影响。 在一个实施例中，在编程过程期间，对于特定字线（或存储元件的其他分组）使用不同的验证电平。 在另一个实施例中，在读取过程期间，不同的比较级别用于特定单词（或存储单元的其他分组）。

公开(公告)号：US20090147569A1

公开(公告)日：2009-06-11

申请号：US12371088

申请日：2009-02-13

Applicant: Jin-Ki KIM

Inventor： Jin-Ki KIM

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3418 ,  G11C16/3427

Abstract: A method for minimizing program disturb in Flash memories. To reduce program disturb in a NAND Flash memory cell string where no programming from the erased state is desired, a local boosted channel inhibit scheme is used. In the local boosted channel inhibit scheme, the selected memory cell in a NAND string where no programming is desired, is decoupled from the other cells in the NAND string. This allows the channel of the decoupled cell to be locally boosted to a voltage level sufficient for inhibiting F-N tunneling when the corresponding wordline is raised to a programming voltage. Due to the high boosting efficiency, the pass voltage applied to the gates of the remaining memory cells in the NAND string can be reduced relative to prior art schemes, thereby minimizing program disturb while allowing for random page programming.

Abstract translation: 一种用于最小化闪存中程序干扰的方法。 为了减少在不需要擦除状态的编程的NAND闪存单元串中的程序干扰，使用局部增强的通道抑制方案。 在本地提升通道禁止方案中，在NAND串中未选择编程的NAND串中选择的存储单元与NAND串中的其它单元解耦。 这使得解耦单元的通道在相应的字线升高到编程电压时被局部提升到足以抑制F-N隧穿的电压电平。 由于高的提升效率，相对于现有技术的方案，可以减少施加到NAND串中的剩余存储单元的栅极的通过电压，从而最小化程序干扰同时允许随机页面编程。

公开(公告)号：US20080225589A1

公开(公告)日：2008-09-18

申请号：US11717550

申请日：2007-03-12

Applicant: Seiichi Aritome ,  Jeffrey C. Antosh ,  Roderick C. Frianeza

Inventor： Seiichi Aritome ,  Jeffrey C. Antosh ,  Roderick C. Frianeza

IPC: G11C16/02

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3427

Abstract: A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells.

Abstract translation: 描述了用于升级多级单元存储器单元中的未选择的存储单元的存储器页升压方法，装置和系统。 存储器装置包括被配置为存储逻辑状态的第一部分和逻辑状态的第二部分的多级单元存储器单元的存储器阵列。 当对逻辑状态的第一部分进行编程时，对未选择的存储器单元施加第一升压处理，并且当对第二部分逻辑状态进行编程时，将第二升压处理应用于未选择的存储器单元。

公开(公告)号：US07408811B2

公开(公告)日：2008-08-05

申请号：US11401937

申请日：2006-04-12

Applicant: Riichiro Shirota ,  Fumitaka Arai

Inventor： Riichiro Shirota ,  Fumitaka Arai

IPC: G11C16/02 ,  G11C16/06

CPC classification number: G11C16/3431 ,  G11C16/0483 ,  G11C16/10

Abstract: A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active areas, each NAND cell unit including a plurality of electrically rewritable and non-volatile memory cells connected in series, both ends of each NAND cell unit being coupled to a source line and a bit line, wherein the device has such a carrier discharging mode as to discharge channel carriers in the NAND cell unit to at least one of the source line and the bit line.

Abstract translation: 半导体存储器件包括：设置在绝缘基板或绝缘层上的半导体层; 在半导体层中限定的有源区域，其中埋设有器件绝缘膜; 以及形成在有源区上的NAND单元单元，每个NAND单元单元包括串联连接的多个电可重写和非易失性存储单元，每个NAND单元单元的两端耦合到源极线和位线，其中， 器件具有这样的载流子放电模式，以将NAND单元单元中的沟道载流子放电到源极线和位线中的至少一个。

公开(公告)号：US20080068890A1

公开(公告)日：2008-03-20

申请号：US11901596

申请日：2007-09-17

Applicant: Silvia Beltrami ,  Angelo Visconti

Inventor： Silvia Beltrami ,  Angelo Visconti

IPC: G11C16/02

CPC classification number: G11C7/02 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/12

Abstract: An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

Abstract translation: 具有NAND架构的闪速存储器件的实施例，包括每个具有可编程阈值电压的数据存储单元矩阵，其中所述矩阵被布置成多个行和列，每行的存储单元连接到 对应的字线和每列的存储单元被布置在多个存储单元串中，每个串中的存储单元串联连接，每列的串耦合到参考电压分配线，该参考电压分配线通过 第一选择器的装置，其中每个串还包括插入在所述串的所述存储单元和所述第一选择器之间的至少一个第一屏蔽元件，所述第一屏蔽元件适于屏蔽所述存储器单元与操作中出现的电场 在存储单元串和第一选择器之间。

公开(公告)号：US07339825B2

公开(公告)日：2008-03-04

申请号：US11258867

申请日：2005-10-27

Applicant: Osamu Iioka ,  Hiroshi Mawatari

Inventor： Osamu Iioka ,  Hiroshi Mawatari

IPC: G11C16/02 ,  G11C8/16 ,  G11C8/12 ,  G11C7/18 ,  G11C16/06

CPC classification number: G11C7/18 ,  G11C7/1012 ,  G11C7/1042 ,  G11C16/0416 ,  G11C16/06 ,  G11C16/24 ,  G11C2207/002 ,  G11C2216/22

Abstract: A nonvolatile semiconductor memory is capable of dual and triple operation with a small chip size. A plurality of sectors is formed. Each sector has nonvolatile memory cells, local bit lines connected to these memory cells, and switch circuits. Write global bit lines and read global bit lines are each wired commonly to the sectors. The write global bit lines transfer write data to the memory cells or verify data from the memory cells. The read global bit lines transfer read data from the memory cells. The switch circuits connect the local bit lines to the write global bit lines or the read global bit lines in accordance with the operation modes. Consequently, it is possible to execute read operation while executing a write sequence or an erase sequence. That is, dual operation can be executed.

Abstract translation: 非易失性半导体存储器能够以小的芯片尺寸进行双重和三次操作。 形成多个扇区。 每个扇区具有非易失性存储单元，连接到这些存储单元的局部位线以及开关电路。 写入全局位线和读取全局位线每个都通常连接到扇区。 写全局位线将写入数据传送到存储单元或从存储单元验证数据。 读取的全局位线从存储器单元传送读取数据。 开关电路根据操作模式将本地位线连接到写全局位线或读全局位线。 因此，可以在执行写入序列或擦除序列时执行读取操作。 也就是说，可以执行双重操作。

公开(公告)号：US20080019183A1

公开(公告)日：2008-01-24

申请号：US11833546

申请日：2007-08-03

Applicant: Dong-Hyuk Chae ,  Dae-Seok Byeon

Inventor： Dong-Hyuk Chae ,  Dae-Seok Byeon

IPC: G11C16/02

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/08

Abstract: Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. The word line driver includes a plurality of pass voltage switches. These switches have outputs electrically coupled by diodes to the plurality of word lines. Methods of programming flash memory devices include applying a pass voltage to a plurality of unselected word lines in a non-volatile memory array while simultaneously applying a sequentially ramped program voltage to a selected word line in the non-volatile memory array. The sequentially ramped program voltage has a minimum value that is clamped by a word line driver to a level not less than a value of the pass voltage.

Abstract translation: 闪存器件包括其中具有多个EEPROM串的NAND串的存储器阵列。 提供字线驱动程序以提高编程效率。 字线驱动器通过多个字线电耦合到存储器阵列。 字线驱动器包括多个通过电压开关。 这些开关具有由二极管电耦合到多个字线的输出。 编程闪速存储器件的方法包括在非易失性存储器阵列中向多个未选择的字线施加通过电压，同时将顺序斜坡的编程电压施加到非易失性存储器阵列中的选定字线。 顺序斜坡编程电压具有被字线驱动器钳位到不小于通过电压值的电平的最小值。

公开(公告)号：US07315472B2

公开(公告)日：2008-01-01

申请号：US11420367

申请日：2006-05-25

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/02 ,  G11C8/12 ,  G11C8/14 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C16/24

Abstract: A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

Abstract translation: 非易失性存储器件可以包括分别与位线串联连接的存储器单元的多个存储器块。 多个存储块中的每一个可以包括具有分别连接到位线的第一选择晶体管和连接到公共源极线的第二选择晶体管之间的第一组存储器单元的第一子存储器块 以及具有分别连接到位线的第三选择晶体管之间的第二组存储单元的第二子存储块以及连接到公共源极线的第四选择晶体管。

公开(公告)号：US20050289313A1

公开(公告)日：2005-12-29

申请号：US11216953

申请日：2005-08-31

Applicant: Frankie Roohparvar

Inventor： Frankie Roohparvar

IPC: G11C16/02 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10 ,  G11C16/20 ,  G11C16/22 ,  G11C16/26

CPC classification number: G11C7/103 ,  G11C7/1018 ,  G11C7/1072 ,  G11C16/20 ,  G11C16/22 ,  G11C16/26

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Abstract translation: 同步闪速存储器包括非易失性存储器单元阵列。 存储器阵列以行和列布置，并且可以进一步布置在可寻址块中。 数据通信连接用于与外部设备（例如处理器或其他存储器控制器）的双向数据通信。 存储器可以在一系列时钟周期期间从数据通信连接上的存储寄存器输出数据，以提供突发的寄存器数据。 存储器还可以根据定义的时钟延迟值提供寄存器数据。 寄存器数据可以包括状态数据，操作设置数据，制造识别和存储器件识别。

公开(公告)号：US20050286313A1

公开(公告)日：2005-12-29

申请号：US11215963

申请日：2005-08-31

Applicant: Andrei Mihnea ,  Chun Chen

Inventor： Andrei Mihnea ,  Chun Chen

IPC: G11C16/02 ,  G11C11/34 ,  G11C16/06 ,  G11C16/14 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

Abstract: Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.