公开(公告)号：US08667365B2

公开(公告)日：2014-03-04

申请号：US12256784

申请日：2008-10-23

Applicant: Nam Phil Jo ,  Dong Hyuk Chae ,  Sung Chung Park ,  Dong Gu Kang

Inventor： Nam Phil Jo ,  Dong Hyuk Chae ,  Sung Chung Park ,  Dong Gu Kang

IPC: G06F11/00

CPC classification number: G11C7/1042 ,  G06F11/1068 ,  G06F13/4239

Abstract: A memory system includes a plurality of memory devices, a controller configured to control the plurality of memory devices, and at least one channel connected between the plurality of memory devices and the controller. The at least one channel includes input/output data lines and control signal lines, which are connected with the plurality of memory devices, and chip enable signal lines respectively connected to each of the plurality of memory devices, wherein the chip enable signal lines enable the plurality of memory devices independently. The controller sends a read command or a program command to one of the plurality of memory devices, and while the one of the plurality of memory devices is performing an internal read operation in response to the read command, the controller reads data from another one of the plurality of memory devices, or while the one of the plurality of memory devices is performing an internal program operation in response to the program command, the controller programs data to another one of the plurality of memory devices.

Abstract translation: 存储器系统包括多个存储器件，被配置为控制多个存储器件的控制器以及连接在多个存储器件与控制器之间的至少一个通道。 所述至少一个通道包括与所述多个存储器件连接的输入/输出数据线和控制信号线以及分别连接到所述多个存储器件中的每一个的芯片使能信号线，其中所述芯片使能信号线使得能够 多个存储设备独立。 控制器向多个存储器件之一发送读取命令或程序命令，并且当多个存储器件中的一个存储器件响应于读取命令执行内部读取操作时，控制器从另一个 多个存储器件，或者当多个存储器件中的一个存储器件响应于程序命令执行内部程序操作时，控制器将数据编程到多个存储器件中的另一个。

公开(公告)号：US08493785B2

公开(公告)日：2013-07-23

申请号：US13465246

申请日：2012-05-07

Applicant: Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

Inventor： Sung-Soo Lee ,  Young-Ho Lim ,  Hyun-Chul Cho ,  Dong-Hyuk Chae

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/26

Abstract: A non-volatile memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储器单元，多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点，具有选择性地连接到感测节点的锁存节点的锁存电路，将锁存节点的逻辑电压设置为编程模式的锁存器输入路径，以及 读取模式和与锁存器输入路径分离的锁存器输出路径。

公开(公告)号：US20130003455A1

公开(公告)日：2013-01-03

申请号：US13561204

申请日：2012-07-30

Applicant: Dong-Hyuk CHAE ,  Young-Ho LIM

Inventor： Dong-Hyuk CHAE ,  Young-Ho LIM

IPC: G11C16/10

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: A nonvolatile semiconductor memory device for an efficient program of multilevel data includes a memory cell array having a plurality of banks and a cache block corresponding to each of the plurality of banks. The cache block has a predetermined data storage capacity. A page buffer is included which corresponds to each of the plurality of banks. A programming circuit programs all of the plurality of banks except a last of said banks with page data. The page data is loaded through each page buffer and programmed into each cache block such that when page data for the last bank is loaded into the page buffer, the loaded page data and the page data programmed into the respective cache blocks are programmed into respective corresponding banks.

Abstract translation: 用于多电平数据的高效程序的非易失性半导体存储器件包括具有多个存储体的存储单元阵列和与多个存储体中的每一个对应的高速缓存块。 高速缓存块具有预定的数据存储容量。 包括对应于多个存储体中的每一个的页面缓冲器。 编程电路使用页面数据对除了最后的所述存储体之外的所有多个存储体进行编程。 页面数据通过每个页面缓冲器加载并被编程到每个缓存块中，使得当最后一个存储体的页面数据被加载到页面缓冲器中时，加载的页面数据和编入各个缓存块中的页面数据被编程到相应的对应的 银行。

公开(公告)号：US08239747B2

公开(公告)日：2012-08-07

申请号：US12216744

申请日：2008-07-10

Applicant: Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

Inventor： Kyoung Lae Cho ,  Jae Hong Kim ,  Yoon Dong Park ,  Jun Jin Kong ,  Dong Hyuk Chae

IPC: G06F11/00

CPC classification number: G06F11/1072 ,  H03M13/09 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/152

Abstract: Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.

Abstract translation: 示例性实施例可以提供存储器件和存储器数据读取方法。 根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位， 以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。 因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

公开(公告)号：US08122329B2

公开(公告)日：2012-02-21

申请号：US12929161

申请日：2011-01-05

Applicant: Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

Inventor： Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

IPC: H03M13/00 ,  G11C29/00

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C11/5628 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract translation: 提供各种读取级别控制装置和方法。 在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及 读数据。 该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

公开(公告)号：US08059467B2

公开(公告)日：2011-11-15

申请号：US12382351

申请日：2009-03-13

Applicant: Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

Inventor： Jae Hong Kim ,  Kyoung Lae Cho ,  Yong June Kim ,  Dong Hyuk Chae

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C2211/5621

Abstract: Memory devices and/or memory programming methods are provided. A memory device may include: a memory cell array including a plurality of memory cells; a programming unit configured to apply a plurality of pulses corresponding to a program voltage to a gate terminal of each of the plurality of memory cells, and to apply a program condition voltage to a bit line connected with a memory cell having a threshold voltage lower than a verification voltage from among the plurality of memory cells; and a control unit configured to increase the program voltage during a first time interval by a first increment for each pulse, and to increase the program voltage during a second time interval by a second increment for each pulse. Through this, it may be possible to reduce a width of a distribution of threshold voltages of a memory cell.

Abstract translation: 提供存储器件和/或存储器编程方法。 存储器件可以包括：包括多个存储器单元的存储单元阵列; 编程单元，被配置为将与编程电压相对应的多个脉冲施加到所述多个存储单元中的每一个的栅极端子，并且将编程状态电压施加到与具有低于阈值电压的阈值电压的存储单元连接的位线 来自所述多个存储单元中的验证电压; 以及控制单元，被配置为在每个脉冲的第一时间间隔期间增加编程电压的第一增量，并且在第二时间间隔期间增加每个脉冲的第二增量的编程电压。 由此，可以减小存储单元的阈值电压分布的宽度。

公开(公告)号：USD644566S1

公开(公告)日：2011-09-06

申请号：US29372872

申请日：2011-01-25

Applicant: Dong Hyuk Chae

Designer： Dong Hyuk Chae

公开(公告)号：US20110205817A1

公开(公告)日：2011-08-25

申请号：US13027439

申请日：2011-02-15

Applicant: Sang Yong YOON ,  Dong Hyuk CHAE ,  Bo Geun KIM

Inventor： Sang Yong YOON ,  Dong Hyuk CHAE ,  Bo Geun KIM

IPC: G11C7/00

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5648

Abstract: A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy.

Abstract translation: 存储器系统包括多位存储器件和控制多位存储器件的存储器控​​制器。 存储器系统确定所请求的程序操作是随机程序操作还是顺序程序操作。 在所请求的程序操作是随机程序操作的情况下，存储器控制器控制多位存储器件根据精细程序关闭策略或精细程序打开策略执行操作。

公开(公告)号：US20110145663A1

公开(公告)日：2011-06-16

申请号：US12929161

申请日：2011-01-05

Applicant: Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

Inventor： Jun Jin Kong ,  Sung Chung Park ,  Dongku Kang ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Nam Phil Jo ,  Seung-Hwan Song

IPC: G06F11/00

CPC classification number: G11C29/42 ,  G06F11/1068 ,  G11C11/5628 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract translation: 提供各种读取级别控制装置和方法。 在各种实施例中，读取级别控制装置可以包括用于对从存储单元读取的数据进行ECC解码的错误控制代码（ECC）解码单元和用于基于ECC解码数据监视误码率（BER）的监视单元，以及 读数据。 该装置还可以包括用于基于所监视的BER来确定读取数据的错误率的错误确定单元，以及用于基于错误率来控制存储单元的读取电平的电平控制单元。

公开(公告)号：US07929346B2

公开(公告)日：2011-04-19

申请号：US12216745

申请日：2008-07-10

Applicant: Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

Inventor： Dong Hun Yu ,  Kyoung Lae Cho ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Jae Hong Kim ,  Seung-Hwan Song

IPC: G11C16/06 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C7/1006 ,  G11C7/14 ,  G11C11/5642 ,  G11C29/00 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50 ,  G11C2211/5634

Abstract: Example embodiments may relate to a method and an apparatus for reading data stored in a memory, for example, providing a method and an apparatus for controlling a reference voltage based on an error of the stored data. Example embodiments may provide a memory data detecting apparatus including a first voltage comparator to compare a threshold voltage of a memory cell with a first reference voltage, a first data determiner to determine a value of at least one data bit stored in the memory cell according to a result of the comparison, an error verifier to verify whether an error occurs in the determined value, a reference voltage determiner to determine a second reference voltage that is lower than the first reference voltage based on a result of the verification, and a second data determiner to re-determine the value of the data based on the determined second reference voltage.

Abstract translation: 示例性实施例可以涉及用于读取存储在存储器中的数据的方法和装置，例如提供一种基于存储的数据的错误来控制参考电压的方法和装置。 示例性实施例可以提供一种存储器数据检测装置，其包括用于将存储器单元的阈值电压与第一参考电压进行比较的第一电压比较器，第一数据确定器，用于根据存储器单元存储的至少一个数据位的值，根据 比较结果，用于验证所确定的值是否发生错误验证器，基于验证结果确定低于第一参考电压的第二参考电压的参考电压确定器，以及第二数据 确定器，以基于所确定的第二参考电压重新确定数据的值。