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    Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation
    4.
    发明授权
    Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation 失效
    非接触均匀隧道分离p-well（CUSP）非易失性存储器阵列架构，制造和操作

    公开(公告)号：US06930350B2

    公开(公告)日：2005-08-16

    申请号：US10655251

    申请日：2003-09-04

    Applicant: Chun Chen ,  Andrei Mihnea ,  Kirk Prall

    Inventor： Chun Chen ,  Andrei Mihnea ,  Kirk Prall

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11519 ,  H01L27/115 ,  H01L27/11521

    Abstract: Floating-gate field-effect transistors or memory cells formed in isolated wells are useful in the fabrication of non-volatile memory arrays and devices. A column of such floating-gate memory cells are associated with a well containing the source/drain regions for each memory cell in the column. These wells are isolated from source/drain regions of other columns of the array. Fowler-Nordheim tunneling can be used to program and erase such floating-gate memory cells either on an individual basis or on a bulk or block basis.

    Abstract translation: 在隔离阱中形成的浮栅场效应晶体管或存储单元在制造非易失性存储器阵列和器件中是有用的。 这种浮栅存储器单元的列与包含列中的每个存储器单元的源极/漏极区的阱相关联。 这些阱与阵列的其他列的源/漏区隔离。 可以使用Fowler-Nordheim隧道来编程和擦除这种浮动栅极存储器单元，无论是单独的还是以块或块为基础的。

    Flash memory cell for high efficiency programming
    5.
    发明授权
    Flash memory cell for high efficiency programming 有权

    公开(公告)号：US06587376B2

    公开(公告)日：2003-07-01

    申请号：US10238317

    申请日：2002-09-10

    Applicant: Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

    Inventor： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

    IPC: G11C1604

    CPC classification number: G11C16/12

    Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

    Flash memory cell for high efficiency programming
    7.
    发明授权
    Flash memory cell for high efficiency programming 有权
    闪存单元，用于高效率编程

    公开(公告)号：US06445619B1

    公开(公告)日：2002-09-03

    申请号：US09920364

    申请日：2001-08-01

    Applicant: Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

    Inventor： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

    IPC: G11C1604

    CPC classification number: G11C16/12

    Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

    Abstract translation: 闪存单元包括栅极，漏极，源极，浮动栅极和控制栅极。 通过向栅极施加第一电压，向漏极施加第二电压，并且通过向漏极施加第三电压，通过在深耗尽区域上诱导约四伏和六伏之间的电压降来对闪存单元进行编程 资源。 在编程操作期间，通道电流大约为零，并且第一电压以与注入电流成比例的速率斜坡化。

    Flash memory cell for high efficiency programming
    8.
    发明授权
    Flash memory cell for high efficiency programming 有权

    公开(公告)号：US06434045B1

    公开(公告)日：2002-08-13

    申请号：US09876674

    申请日：2001-06-07

    Applicant: Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

    Inventor： Andrei Mihnea ,  Paul J. Rudeck ,  Chun Chen

    IPC: G11C1604

    Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

    Flash memory
    9.
    发明授权
    Flash memory 有权
    闪存

    公开(公告)号：US07272044B2

    公开(公告)日：2007-09-18

    申请号：US11217920

    申请日：2005-09-01

    Applicant: Andrei Mihnea ,  Chun Chen

    Inventor： Andrei Mihnea ,  Chun Chen

    IPC: G11C11/34

    CPC classification number: G11C16/16 ,  G11C16/08 ,  G11C16/14 ,  H01L27/115

    Abstract: Flash memory supporting methods for erasing memory cells using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period.

    Abstract translation: 闪速存储器支持方法，用于使用第一极性的源极电压的幅度的减小来擦除存储器单元，以在擦除周期期间增加第二极性的控制栅极电压的幅度。

    Method for erasing an NROM cell
    10.
    发明授权
    Method for erasing an NROM cell 有权
    擦除NROM单元的方法

    公开(公告)号：US07227787B2

    公开(公告)日：2007-06-05

    申请号：US11415446

    申请日：2006-05-01

    Applicant: Andrei Mihnea ,  Chun Chen

    Inventor： Andrei Mihnea ,  Chun Chen

    IPC: G11C11/34 ,  G11C16/04

    CPC classification number: G11C16/3404 ,  G11C16/0466 ,  G11C16/14 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/345 ,  G11C2216/18

    Abstract: An operation to erase a nitride read only memory (NROM) memory block starts by erasing the memory block. An erase verify operation can then be performed to determine the success of the erase. If a read operation is performed and column current is detected, a high-efficiency recovery operation is performed. If the read operation is performed and column current is not detected, the erase operation has been successfully completed.

    Abstract translation: 通过擦除存储块来开始擦除氮化物只读存储器（NROM）存储器块的操作。 然后可以执行擦除验证操作以确定擦除的成功。 如果执行读取操作并且检测到列电流，则执行高效率恢复操作。 如果执行了读取操作，并且未检测到列电流，则擦除操作已成功完成。

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