公开(公告)号：US08619472B2

公开(公告)日：2013-12-31

申请号：US13281312

申请日：2011-10-25

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/22

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3427

Abstract: A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state.

Abstract translation: 一种用于操作闪速存储器件的方法包括将通过电压施加到漏极通过字线，源极字线和未选字线。 漏极通行字线设置在漏极选择线和字线之间。 漏极字线具有与字线相同的结构。 在源选择线和字线之间提供源通过字线。 源通道字线具有与字线相同的结构。 将编程电压施加到与所选择的存储器单元块相关联的选定字线。 接地电压被施加到漏通字线和源通路字线。 与未选择的存储单元块相关联的字线设置为浮动状态。

公开(公告)号：US20110261623A1

公开(公告)日：2011-10-27

申请号：US13095156

申请日：2011-04-27

Applicant: Hea Jong YANG ,  Hee Youl Lee ,  Sung Jae Chung ,  Hyun Heo ,  Jeong Hyong Yi ,  Yong Dae Park

Inventor： Hea Jong YANG ,  Hee Youl Lee ,  Sung Jae Chung ,  Hyun Heo ,  Jeong Hyong Yi ,  Yong Dae Park

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/16 ,  G11C16/32

Abstract: A method of erasing a semiconductor memory device comprises grouping a plurality of word lines of each memory block into at least two groups based on intensity of disturbance between neighboring word lines; performing an erase operation by applying a ground voltage to all word lines of a selected memory block and by applying an erase voltage to a well of the selected memory block; and first increasing the ground voltage of one group of the groups to a positive voltage during the erase operation.

Abstract translation: 擦除半导体存储器件的方法包括：基于相邻字线之间的干扰强度将每个存储器块的多个字线分组成至少两组; 通过对所选择的存储块的所有字线施加接地电压并通过向所选存储块的阱施加擦除电压来执行擦除操作; 并且在擦除操作期间首先将一组组的接地电压增加到正电压。

公开(公告)号：US08045372B2

公开(公告)日：2011-10-25

申请号：US11760767

申请日：2007-06-10

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/06 ,  G11C16/08 ,  G11C16/22

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3427

Abstract: A flash memory device includes a plurality of memory cell blocks, an operating voltage generator, a block switching unit and a voltage supply circuit. Each of the plurality of memory cell blocks includes select lines and word lines, and has pass word lines included between the select lines and the word lines. The operating voltage generator outputs operating voltages to global select lines, global word lines and global pass word lines. The block switching unit connects the global word lines to the word lines and the select lines in response to a block select signal. The voltage supply circuit is connected to the select line and the pass word line, and is configured to supply the select line and the pass word line with a ground voltage in response to a block select inverse signal.

Abstract translation: 闪存器件包括多个存储单元块，工作电压发生器，块切换单元和电压供应电路。 多个存储单元块中的每一个都包括选择线和字线，并且具有包括在选择线和字线之间的字线。 工作电压发生器将工作电压输出到全局选择线，全局字线和全局通过字线。 块切换单元响应于块选择信号将全局字线连接到字线和选择线。 电压供给电路连接到选择线和通过字线，并且被配置为响应于块选择反相信号而将选择线和通过字线提供接地电压。

公开(公告)号：US20100072560A1

公开(公告)日：2010-03-25

申请号：US12562727

申请日：2009-09-18

Applicant: Hee Youl Lee ,  Jae Yoon Noh

Inventor： Hee Youl Lee ,  Jae Yoon Noh

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/26586 ,  H01L27/11521 ,  H01L27/11529 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed.

Abstract translation: 一种制造非易失性存储器件的方法，其中在半导体衬底上形成第一栅极线和第二栅极线。 第一栅极线以第一宽度彼此间隔开，第二栅极线以第二宽度彼此间隔开，并且第一宽度比第二宽度宽。 执行在第一栅极线和第二栅极线之间的半导体衬底中形成第一结区域的第一离子注入工艺。 然后执行在第一栅极线之间的各个第一结区域中形成第二结区域的第二离子注入工艺。

公开(公告)号：US07643338B2

公开(公告)日：2010-01-05

申请号：US11618697

申请日：2006-12-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C11/34 ,  G11C11/04

CPC classification number: G11C16/0483

Abstract: A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied.

Abstract translation: 一种用于对闪速存储器件进行编程的方法包括将程序偏置应用于存储单元串内的多个存储单元的存储单元。 每个存储器单元串包括源选择线，多个存储单元和漏极选择线。 相对于已经应用了程序偏置的存储单元，在源选择线方向中的至少一个存储单元施加第一通过偏压。 相对于已经施加了第一通过偏压的存储单元，在漏选择线方向上对存储单元施加第二偏压。

公开(公告)号：US07616486B2

公开(公告)日：2009-11-10

申请号：US11965974

申请日：2007-12-28

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C11/34

CPC classification number: G11C16/24

Abstract: A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line.

Abstract translation: 闪存器件的单元阵列包括第一和第二存储器块单元和电压发生器。 第一和第二存储块单元中的每一个包括具有多个存储单元的多个存储块。 电压发生器向第一和第二存储器单元输出源电压，电源电压和正偏压。 第一和第二存储器块单元通过位线并联连接。

公开(公告)号：US20090168510A1

公开(公告)日：2009-07-02

申请号：US12147165

申请日：2008-06-26

Applicant: Hee Youl Lee ,  Won Sic Woo

Inventor： Hee Youl Lee ,  Won Sic Woo

IPC: G11C16/06

CPC classification number: G11C16/34 ,  G11C16/10 ,  G11C16/3454

Abstract: The present invention relates to an operation of a non-volatile memory device. According to a method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting a memory block. As a result of the first program operation, threshold voltages of the memory cells are firstly measured. A second program operation is performed using a second program voltage, which is increased as much as a difference between a first threshold voltage, that is, a lowest voltage level of the firstly measured threshold voltages and a second threshold voltage, that is, an intermediate voltage level of the firstly measured threshold voltages. The second program operation is repeatedly performed by increasing the second program voltage as much as the difference between the first and second threshold voltages until the lowest threshold voltage becomes higher than a program verify voltage. A pass voltage is then set by reflecting a first voltage level, that is, a difference between a program voltage applied in a last program execution step and the first program voltage.

Abstract translation: 本发明涉及一种非易失性存储器件的操作。 根据本发明的一个方面的操作非易失性存储器件的方法，通过对构成存储器块的存储器单元的字线应用第一编程电压来执行第一编程操作。 作为第一编程操作的结果，首先测量存储单元的阈值电压。 使用第二编程电压执行第二编程操作，该第二编程电压被增加到第一阈值电压（即，首先测量的阈值电压的最低电压电平）与第二阈值电压之间的差，即中间 首先测量的阈值电压的电压电平。 通过将第二编程电压与第一和第二阈值电压之间的差异增加直到最低阈值电压变得高于编程验证电压来重复执行第二编程操作。 然后通过反映第一电压电平，即在最后程序执行步骤中施加的编程电压与第一编程电压之间的差异来设置通过电压。

公开(公告)号：US07315472B2

公开(公告)日：2008-01-01

申请号：US11420367

申请日：2006-05-25

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/02 ,  G11C8/12 ,  G11C8/14 ,  G11C5/06

CPC classification number: G11C16/0483 ,  G11C16/24

Abstract: A non-volatile memory device may include a plurality of memory blocks including memory cells connected in series to bit lines, respectively. Each of the plurality of memory blocks may include a first sub memory block having a first group of memory cells, which are respectively connected in series between first select transistors connected to the bit lines, respectively, and second select transistors connected to a common source line, and a second sub memory block having a second group of memory cells, which are respectively connected in series between third select transistors connected to the bit lines, respectively, and fourth select transistors connected to the common source line.

Abstract translation: 非易失性存储器件可以包括分别与位线串联连接的存储器单元的多个存储器块。 多个存储块中的每一个可以包括具有分别连接到位线的第一选择晶体管和连接到公共源极线的第二选择晶体管之间的第一组存储器单元的第一子存储器块 以及具有分别连接到位线的第三选择晶体管之间的第二组存储单元的第二子存储块以及连接到公共源极线的第四选择晶体管。

公开(公告)号：US06934193B2

公开(公告)日：2005-08-23

申请号：US10364137

申请日：2003-02-11

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: H01L21/8247 ,  G11C16/14 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04

CPC classification number: G11C11/14 ,  G11C16/14 ,  G11C16/16

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a positive bias voltage is applied to the control gate, the source and drain are floated, a negative bias voltage is applied to the well, a ground voltage is then applied to the well while maintaining the positive bias voltage at the control gate, and subsequently a ground voltage is applied to the control gate.

Abstract translation: 公开了一种用于擦除闪存单元的方法，包括：（a）半导体衬底，（b）栅极，（c）源极，（d）漏极（e）阱，所述栅极包括：（1） 隧道氧化膜，（2）浮栅，（3）电介质膜和（4）堆叠在半导体衬底上的控制栅。 在所公开的方法之一中，将正偏置电压施加到控制栅极，源极和漏极浮置，将负偏压施加到阱，然后将接地电压施加到阱，同时保持正偏置电压 在控制栅极处，然后将接地电压施加到控制栅极。

公开(公告)号：US06339006B1

公开(公告)日：2002-01-15

申请号：US09609337

申请日：2000-06-30

Applicant: Min Kyu Lee ,  Hee Hyun Chang ,  Hee Youl Lee ,  Dong Kee Lee

Inventor： Min Kyu Lee ,  Hee Hyun Chang ,  Hee Youl Lee ,  Dong Kee Lee

IPC: H01L21331

CPC classification number: H01L29/7887 ,  G11C11/5621 ,  G11C16/0458 ,  G11C2211/5612 ,  H01L21/28273

Abstract: The invention relates to a flash EEPROM cell and method of manufacturing the same. The method of manufacturing a flash EEPROM cell includes sequentially forming a tunnel oxide film, a polysilicon layer for a floating gate and a hard mask layer on a semiconductor substrate; patterning the hard mask layer and then forming a hard mask layer spacer at the etching side of the patterned hard mask layer; removing the exposed portion of the polysilicon layer for the floating gate by etching process using the patterned hard mask layer and the hard mask layer spacer as etching masks thus to form first and second patterns that are separated in two; removing the patterned hard mask layer and the hard mask layer spacer and then depositing a dielectric film and a polysilicon layer for a control gate on the entire structure, thus forming a first floating gate, a second floating gate and a control gate by self-aligned etching process; and forming a drain junction and a source junction by cell source/drain ion implantation process. Thus, the present invention can prevent lower of the quality of the tunnel oxide film and thus increase the coupling ratio.

Abstract translation: 本发明涉及一种快闪EEPROM单元及其制造方法。 制造快闪EEPROM单元的方法包括在半导体衬底上依次形成隧道氧化膜，浮栅的多晶硅层和硬掩模层; 图案化硬掩模层，然后在图案化硬掩模层的蚀刻侧形成硬掩模层间隔物; 通过使用图案化的硬掩模层和硬掩模层间隔物作为蚀刻掩模的蚀刻工艺去除用于浮置栅极的多晶硅层的暴露部分，从而形成两个分离的第一和第二图案; 去除图案化的硬掩模层和硬掩模层间隔物，然后在整个结构上沉积用于控制栅极的电介质膜和多晶硅层，从而通过自对准形成第一浮栅，第二浮栅和控制栅 蚀刻工艺; 以及通过电池源/漏离子注入工艺形成漏极结和源极结。 因此，本发明可以防止隧道氧化膜的质量降低，从而增加耦合比。