公开(公告)号：US20240379853A1

公开(公告)日：2024-11-14

申请号：US18782106

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Shih-Chieh Chang

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49

Abstract: A FinFET device and a method of forming the same are provided. The method includes forming semiconductor strips over a substrate. Isolation regions are formed over the substrate and between adjacent semiconductor strips. A first recess process is performed on the isolation regions to expose first portions of the semiconductor strips. The first portions of the semiconductor strips are reshaped to form reshaped first portions of the semiconductor strips. A second recess process is performed on the isolation regions to expose second portions of the semiconductor strips below the reshaped first portions of the semiconductor strips. The second portions of the semiconductor strips are reshaped to form reshaped second portions of the semiconductor strips. The reshaped first portions of the semiconductor strips and the reshaped second portions of the semiconductor strips form fins. The fins extend away from topmost surfaces of the isolation regions.

公开(公告)号：US20240379812A1

公开(公告)日：2024-11-14

申请号：US18784647

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region of a substrate. The gate stack includes a gate dielectric layer and a first work function layer over the gate dielectric layer. The first work function layer includes a plurality of first layers and a plurality of second layers arranged in an alternating manner over the gate dielectric layer. The plurality of first layers include a first material. The plurality of second layers include a second material different from the first material.

公开(公告)号：US20240379798A1

公开(公告)日：2024-11-14

申请号：US18781506

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Cheng-Hao Hou ,  Che-Hao Chang ,  Da-Yuan Lee ,  Chi On Chui

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/49 ,  H01L29/51 ,  H01L29/786

Abstract: In an embodiment, a device includes: a first gate dielectric on a first channel region of a first semiconductor feature; a first gate electrode on the first gate dielectric; a second gate dielectric on a second channel region of a second semiconductor feature, the second gate dielectric having a greater crystallinity than the first gate dielectric; and a second gate electrode on the second gate dielectric.

公开(公告)号：US20240379789A1

公开(公告)日：2024-11-14

申请号：US18781147

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Liang Chu ,  Chien-Chih Chou ,  Chih-Chang Cheng ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Ta-Yuan Kung

IPC: H01L29/423 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

公开(公告)号：US20240379758A1

公开(公告)日：2024-11-14

申请号：US18196223

申请日：2023-05-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Yip LOH ,  Hong-Mao LEE ,  Harry CHIEN ,  Po-Chin CHANG ,  Sung-Li WANG ,  Jhih-Rong HUANG ,  Tzer-Min SHEN ,  Chih-Wei CHANG

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/20 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure and methods of forming the same are described. In some embodiments, the structure includes an N-type source/drain epitaxial feature disposed over a substrate, a P-type source/drain epitaxial feature disposed over the substrate, a first silicide layer disposed directly on the N-type source/drain epitaxial feature, and a second silicide layer disposed directly on the P-type source/drain epitaxial feature. The first and second silicide layers include a first metal, and the second silicide layer is substantially thicker than the first silicide layer. The structure further includes a third silicide layer disposed directly on the first silicide layer and a fourth silicide layer disposed directly on the second silicide layer. The third and fourth silicide layer include a second metal different from the first metal, and the third silicide layer is substantially thicker than the fourth silicide layer.

公开(公告)号：US20240379679A1

公开(公告)日：2024-11-14

申请号：US18314245

申请日：2023-05-09

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Junjing Bao ,  Jun Yuan

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775

Abstract: A 3D dual complementary-circuit structure includes a first forksheet structure stacked on a first side of, in a first direction, a second forksheet structure to provide two complementary circuits in a space of a single forksheet structure. A dividing wall bisects at least one semiconductor slab in the first forksheet structure into a first slab portion with a first semiconductor type and a second slab portion with a second semiconductor type and also bisects at least one semiconductor slab in the second forksheet structure into a third slab portion with a third semiconductor type and a fourth slab portion with a fourth semiconductor type. One of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type may be a same semiconductor type as the first semiconductor type. Two complementary metal oxide semiconductor (CMOS) circuits may be formed in the area of a single forksheet structure.

公开(公告)号：US20240379677A1

公开(公告)日：2024-11-14

申请号：US18784098

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhon Jhy Liaw

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes doping a substrate with a dopant to form a first well region of a first circuit and a second well region of a second circuit, forming first and second active regions respectively over the first and second well regions, forming a first gate stack engaging the first active region and a second gate stack engaging the second active region, and forming a first source/drain (S/D) feature adjoining the first active region and a second S/D feature adjoining the second active region. The first gate stack has a gate pitch less than the second gate stack. The first S/D feature has a depth smaller than the second S/D feature.

公开(公告)号：US20240379448A1

公开(公告)日：2024-11-14

申请号：US18783632

申请日：2024-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.

公开(公告)号：US20240371964A1

公开(公告)日：2024-11-07

申请号：US18774210

申请日：2024-07-16

Applicant: Shahaji B. More ,  Chandrashekhar Prakash Savant ,  Tien-Wei Yu ,  Chia-Ming Tsai

Inventor： Shahaji B. More ,  Chandrashekhar Prakash Savant ,  Tien-Wei Yu ,  Chia-Ming Tsai

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A device includes a semiconductor region, an interfacial layer over the semiconductor region, the interfacial layer including a semiconductor oxide, a high-k dielectric layer over the interfacial layer, and an intermixing layer over the high-k dielectric layer. The intermixing layer includes oxygen, a metal in the high-k dielectric layer, and an additional metal. A work-function layer is over the intermixing layer. A filling-metal region is over the work-function layer.

公开(公告)号：US20240363726A1

公开(公告)日：2024-10-31

申请号：US18765932

申请日：2024-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chin-Hsiang Lin ,  Teng-Chun TSAI ,  Huang-Lin Chao ,  Akira Mineji

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66515 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.