公开(公告)号：US20240321637A1

公开(公告)日：2024-09-26

申请号：US18652803

申请日：2024-05-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Lin Chuang ,  Chia-Hao Chang ,  Sheng-Tsung Wang ,  Lin-Yu Huang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L21/76897 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283

摘要： The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.

公开(公告)号：US20240321634A1

公开(公告)日：2024-09-26

申请号：US18606424

申请日：2024-03-15

申请人： Sumitomo Electric Industries, Ltd.

发明人： Yukihiro TSUJI

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L21/76876 ,  H01L21/76879 ,  H01L23/5226 ,  H01L29/452 ,  H01L29/475 ,  H01L29/66462 ,  H01L29/7786

摘要： A transistor includes a semiconductor stack portion, a source electrode, a drain electrode, a gate electrode, a first polysilicon film, a dielectric layer, a first plug, and a first wiring. The source electrode and the drain electrode are provided on the semiconductor stack portion. The gate electrode is provided between the source electrode and the drain electrode on the semiconductor stack portion. The first polysilicon film is provided on a first electrode that is one of the gate electrode, the source electrode, and the drain electrode. The dielectric layer is provided on the semiconductor stack portion and covers the gate electrode, the source electrode, the drain electrode, and the first polysilicon film. The dielectric layer has a first opening formed on the first polysilicon film. The first plug contains tungsten, is embedded in the first opening, and is in contact with the first polysilicon film.

公开(公告)号：US12100730B2

公开(公告)日：2024-09-24

申请号：US18501396

申请日：2023-11-03

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Po-Chia Lai ,  Stefan Rusu ,  Chun-Yen Lee

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L27/08 ,  H01L49/02

CPC分类号： H01L28/60 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0805

摘要： Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

公开(公告)号：US12100649B2

公开(公告)日：2024-09-24

申请号：US17482294

申请日：2021-09-22

申请人： QUALCOMM Incorporated

发明人： Chien-Te Feng ,  Wen Yin ,  Jay Scott Salmon

IPC分类号： H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/522 ,  H01L23/60

CPC分类号： H01L23/5226 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/60 ,  H01L24/20

摘要： A device comprising a package and a board. The package includes a substrate comprising a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back side metal layer coupled to a back side of the integrated device, a first solder interconnect coupled to the back side metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package through the plurality of solder interconnects. The first solder interconnect is coupled to the board.

公开(公告)号：US12100648B2

公开(公告)日：2024-09-24

申请号：US18234695

申请日：2023-08-16

申请人： SILICONWARE PRECISION INDUSTRIES CO., LTD.

发明人： Ho-Chuan Lin ,  Chia-Chu Lai ,  Min-Han Chuang

IPC分类号： H01L23/522 ,  H01L23/31 ,  H01L49/02

CPC分类号： H01L23/5223 ,  H01L23/31 ,  H01L23/5226 ,  H01L28/40

摘要： An electronic module is provided, in which a first metal layer, an insulating layer and a second metal layer are sequentially formed on side faces and a non-active face of an electronic component to serve as a capacitor structure, where the capacitor structure is exposed from an active face of the electronic component so that by directly forming the capacitor structure on the electronic component, a distance between the capacitor structure and the electronic component is minimized, such that the effect of suppressing impedance can be optimized.

公开(公告)号：US12100628B2

公开(公告)日：2024-09-24

申请号：US17843727

申请日：2022-06-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/08

CPC分类号： H01L21/823871 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0924 ,  H01L29/0847

摘要： Interconnect structures and corresponding formation techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary interconnect structure for a FinFET includes a gate node via electrically coupled to a gate of the FinFET, a source node via electrically coupled to a source of the FinFET, and a drain node via electrically coupled to a drain of the FinFET. A source node via dimension ratio defines a longest dimension of the source node via relative to a shortest dimension of the source node via, and a drain node via dimension ratio defines a longest dimension of the drain node via relative to a shortest dimension of the drain node via. The source node via dimension ratio is greater than the drain node via dimension ratio. In some implementations, the source node via dimension ratio is greater than 2, and the drain node via dimension ratio is less than 1.2.

公开(公告)号：US20240314996A1

公开(公告)日：2024-09-19

申请号：US18672076

申请日：2024-05-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jhon-Jhy LIAW

IPC分类号： H10B10/00 ,  H01L21/027 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092

CPC分类号： H10B10/12 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228 ,  H01L23/53257 ,  H01L21/0274 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/0924 ,  H01L27/0928

摘要： Semiconductor structures are provided. A semiconductor structure includes a memory cell and a logic cell. The memory cell includes a latch circuit, a pass-gate transistor coupling an output of the latch circuit to a bit line, and a first etching stop layer formed on the bit line. A first source/drain region of the pass-gate transistor is electrically connected to the bit line. A second source/drain region of a transistor of the logic cell is electrically connected to a local interconnect line. A second etching stop layer is formed on the local interconnect line. Bottom surfaces of the bit line and the local interconnect line are coplanar. A bottom surface of the first etching stop layer is in contact with a top surface of the bit line, and a bottom surface of the second etching stop layer is in contact with a top surface of the local interconnect line.

公开(公告)号：US20240312930A1

公开(公告)日：2024-09-19

申请号：US18673328

申请日：2024-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kai-Ming Ching ,  Shu-Shen Yeh ,  Chien-Hung Chen ,  Hui-Chang Yu ,  Yu-Min Cheng

IPC分类号： H01L23/552 ,  H01L21/50 ,  H01L23/00 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

CPC分类号： H01L23/552 ,  H01L21/50 ,  H01L23/16 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/08 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/165 ,  H01L2224/08113 ,  H01L2224/16227 ,  H01L2224/17051 ,  H01L2224/32245 ,  H01L2924/16195

摘要： A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

公开(公告)号：US20240312928A1

公开(公告)日：2024-09-19

申请号：US18673099

申请日：2024-05-23

申请人： Invensas LLC

发明人： Patrick Variot ,  Hong Shen

IPC分类号： H01L23/552 ,  H01L23/31 ,  H01L23/522

CPC分类号： H01L23/552 ,  H01L23/31 ,  H01L23/5226

摘要： A microelectronic device may include a substrate, a first chip on the substrate, and a second chip on the substrate. A plurality of pillars may be located between the first chip and the second chip, wherein a first end of each pillar of the plurality of pillars is adjacent to the substrate. A spacing among the plurality of pillars is at least equal to a distance sufficient to block electromagnetic interference (EMI) and/or radio frequency interference (RFI) between the first chip and the second chip. The microelectronic device may also include a cover over at least the first chip, the second chip, and the plurality of pillars, wherein a second end of each pillar of the plurality of pillars is at least adjacent to a trench defined within the cover. The trench may include a conductive material therein.

公开(公告)号：US20240312902A1

公开(公告)日：2024-09-19

申请号：US18474345

申请日：2023-09-26

申请人： Samsung Electronics Co., Ltd.

发明人： Donghoon Kwon

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC分类号： H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

摘要： A three-dimensional semiconductor memory device comprises a first substrate including a cell array region and a contact region, a stack structure including interlayer dielectric layers and gate electrodes on the first substrate, a second dielectric layer on the stack structure, a cell contact plug that extends through the second dielectric layer and the contact region, a selection mold structure on the stack structure and the second dielectric layer, a third dielectric layer on the selection mold structure, and a capping through contact and a dummy through contact that extend through the selection mold structure and are connected to the cell contact plug. The dummy through contact has a second width. The capping through contact has a first width. The second width is different from the first width.