公开(公告)号：US20170337985A1

公开(公告)日：2017-11-23

申请号：US15597820

申请日：2017-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindita BORAH ,  Muthusubramanian VENKATESWARAN ,  Kushal D. MURTHY ,  Vikram GAKHAR ,  Preetam TADEPARTHY

IPC: G11C29/38 ,  G11C14/00 ,  G11C17/08 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/12 ,  G11C29/36

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

公开(公告)号：US20170323222A1

公开(公告)日：2017-11-09

申请号：US15467775

申请日：2017-03-23

Applicant: Invecas, Inc.

Inventor： Venkata N.S.N. Rao ,  Ravindra Kantamani ,  Prasad Chalasani

IPC: G06N99/00 ,  G11C7/22

CPC classification number: G06N99/005 ,  G11C5/063 ,  G11C7/00 ,  G11C7/1066 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/10 ,  G11C29/36 ,  G11C2029/3602 ,  G11C2207/2254

Abstract: An optimized method, system, and apparatus for determining optimal DQS delay for DDR memory interfaces are disclosed. The method performs data eye training in a two dimensional space with time delay value as x-axis and reference voltage (Vref) as y-axis to determine a rectangular data eye within an overall data eye with Vref margin.

公开(公告)号：US09810739B2

公开(公告)日：2017-11-07

申请号：US14924682

申请日：2015-10-27

Applicant: ANDES TECHNOLOGY CORPORATION

Inventor： Zhong-Ho Chen

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/00

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318588 ,  G11C29/00 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C29/46 ,  G11C29/56012 ,  G11C2029/5602

Abstract: An electronic system, a system diagnostic circuit, and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data to the instruction register circuit or the data register circuit according to an operating state. The detect circuit update the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.

公开(公告)号：US09715942B2

公开(公告)日：2017-07-25

申请号：US14734041

申请日：2015-06-09

Applicant: International Business Machines Corporation

Inventor： Aravindan J. Busi ,  Deepak I. Hanagandi ,  Krishnendu Mondal ,  Michael R. Ouellette

IPC: G01R31/28 ,  G11C29/18 ,  G11C29/36 ,  G11C29/38

CPC classification number: G11C29/18 ,  G11C29/36 ,  G11C29/38

Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.

公开(公告)号：US20170200509A1

公开(公告)日：2017-07-13

申请号：US15324404

申请日：2014-07-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Anys Bacha

IPC: G11C29/38 ,  G11C29/36

CPC classification number: G11C29/38 ,  G06F11/3676 ,  G11C29/36

Abstract: A template of instructions may be copied from a non-volatile memory (NVM) to a plurality of cache lines of an instruction cache of a processor. The instructions of the templates copied to the instruction cache may be executed. The templates may include a conditional branch instruction to determine if to proceed to a next template of the plurality of copied templates.

公开(公告)号：US20170178750A1

公开(公告)日：2017-06-22

申请号：US15384843

申请日：2016-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUKYONG KANG ,  HANGI JUNG ,  Hun-Dae CHOI

IPC: G11C29/38 ,  G11C11/4093 ,  G11C11/4074 ,  G11C29/36

CPC classification number: G11C29/38 ,  G06F13/4086 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4093 ,  G11C16/34 ,  G11C29/025 ,  G11C29/36 ,  G11C29/50008

Abstract: A memory module includes a first memory device including a first one-die termination circuit for impedance matching of a signal path and a second memory device sharing the signal path with the first memory device and including a second on-die termination circuit for impedance matching of the signal path, wherein the signal path corresponds to a command or address signal path provided from a host, and the first and second on-die termination circuits are individually controlled according to control of the host.

公开(公告)号：US09672939B2

公开(公告)日：2017-06-06

申请号：US14518734

申请日：2014-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael A. Shore

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/38 ,  G11C29/36

CPC classification number: G11C29/44 ,  G11C29/36 ,  G11C29/38 ,  G11C29/4401 ,  G11C29/883 ,  G11C2229/723

Abstract: Testing systems and methods, as well as memory devices using such testing systems and methods, may facilitate testing of memory devices using a read-modify-write test procedure. One such testing system receives a signal indicative of at least some of a plurality of bits of data read from an address differing from each other, and then masks subsequent write operations at the same address. Therefore, any address at which the bits of read data do not all have the same value may be considered to be faulty. Failure data from the test can therefore be stored in the same array of memory cells that is being tested.

公开(公告)号：US09666291B2

公开(公告)日：2017-05-30

申请号：US14899361

申请日：2014-05-22

Applicant: INDUSTRIAL BANK OF KOREA

Inventor： Insun Park

IPC: G11C16/04 ,  G11C16/16 ,  G11C29/10 ,  G11C29/36 ,  G11C29/00 ,  G11C29/16 ,  G11C29/18

CPC classification number: G11C16/16 ,  G11C29/00 ,  G11C29/10 ,  G11C29/16 ,  G11C29/18 ,  G11C29/36

Abstract: Disclosed is a memory test method including receiving a memory test command, receiving pattern information for generating a data pattern to be written in a memory cell, and programming the memory cell according to the pattern information. According to this method, it is not required to receive external data to be programmed in a cell array.

公开(公告)号：US20170148530A1

公开(公告)日：2017-05-25

申请号：US15423692

申请日：2017-02-03

Applicant: Seagate Technology LLC

Inventor： Zhengang Chen ,  David Patmore ,  Yingji Ju ,  Erich F. Haratsch

IPC: G11C29/42 ,  G11C29/44 ,  H03M13/11 ,  G11C29/36

CPC classification number: G11C29/42 ,  G06F3/064 ,  G06F11/00 ,  G11C7/10 ,  G11C11/5628 ,  G11C16/00 ,  G11C16/10 ,  G11C29/36 ,  G11C29/44 ,  G11C29/52 ,  H03M13/1108 ,  H04L1/00

Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.

公开(公告)号：US09659669B2

公开(公告)日：2017-05-23

申请号：US14698219

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.