公开(公告)号：US20170229192A1

公开(公告)日：2017-08-10

申请号：US15498855

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/42 ,  G11C11/4094 ,  G11C29/00 ,  G11C11/4078 ,  G11C17/16 ,  G11C17/18 ,  G11C29/36 ,  G11C11/4096

CPC classification number: G11C29/4401 ,  G01R31/3187 ,  G06F11/2053 ,  G06F11/27 ,  G11B20/1816 ,  G11C5/04 ,  G11C8/06 ,  G11C8/10 ,  G11C11/40 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/36 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56008 ,  G11C29/78 ,  G11C29/785 ,  G11C2029/4402 ,  G11C2029/5606

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09524770B2

公开(公告)日：2016-12-20

申请号：US15142491

申请日：2016-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC: G11C7/00 ,  G11C11/406 ,  G11C17/16 ,  G11C29/44 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

公开(公告)号：US09460766B2

公开(公告)日：2016-10-04

申请号：US14801707

申请日：2015-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Yoon Lee ,  Myeong-O Kim ,  Kyo-Min Sohn ,  Sang-Joon Hwang

IPC: G11C7/00 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C7/12 ,  G11C11/4076 ,  G11C11/4094

Abstract: A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.

Abstract translation: 存储器件可以包括预充电控制电路，有源控制电路和驱动器电路。 预充电控制电路可以被配置为在接收到用于第一组的预充电命令之后接收有效命令，在接收到活动命令时确定第一组的预充电操作是否已经结束，并且生成 根据确定的结果激活指令信号。 有源控制电路可以被配置为根据有效指令信号产生用于有效操作的有效控制信号。 驱动器电路可以被配置为根据主动控制信号来控制有效操作。

公开(公告)号：US09171605B1

公开(公告)日：2015-10-27

申请号：US14103794

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sik Kim ,  Won-Il Bae ,  Myeong-O Kim ,  Min-Soo Kim ,  Ho-Seok Seol ,  Min-Sang Park ,  Kyo-Min Sohn ,  Chi-Hwan Lee ,  Sang-Joon Hwang

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G06F12/1018 ,  G11C7/00 ,  G11C11/402 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/408

Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Abstract translation: 提供了使用n位地址来检测半导体器件的集中地址的方法。 该方法包括：对于k组中的每一组，将n位地址划分为k个组，其中n和k中的每一个是等于或大于2的整数，检测对应于该组的一个或多个集中子地址，以及 通过组合用于k个组的一个或多个集中子地址来生成至少一个集中地址。

公开(公告)号：US11169711B2

公开(公告)日：2021-11-09

申请号：US16524749

申请日：2019-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung Kim ,  Young-Hoon Son ,  Chan-Kyung Kim ,  Ho-Young Song ,  Jung Ho Ahn ,  Sang-Joon Hwang

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US09298612B2

公开(公告)日：2016-03-29

申请号：US14015536

申请日：2013-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Sung Shin ,  Sang-Joon Hwang ,  Seung-Man Shin ,  In-Su Choi ,  Jung-Ho Jung

IPC: G06F13/38 ,  G06F12/06 ,  G11C11/00 ,  G06F3/00 ,  G11C29/44

CPC classification number: G06F12/06 ,  G06F2212/205 ,  G11C11/005 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Abstract translation: 半导体存储器件包括第一类型存储器的第一存储器块; 以及具有与第一类型不同类型的第二类型存储器的第二存储块。 第一存储块的第一地址区和第二存储块的第二地址区被包括在相同的地址域中。 第一和第二存储块中的每一个被包括地址域的地址的地址信号访问，而第二存储块是非易失性存储器。

公开(公告)号：US10416896B2

公开(公告)日：2019-09-17

申请号：US15603255

申请日：2017-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Il O ,  Nam Sung Kim ,  Young-Hoon Son ,  Chan-Kyung Kim ,  Ho-Young Song ,  Jung Ho Ahn ,  Sang-Joon Hwang

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/16

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

公开(公告)号：US10347355B2

公开(公告)日：2019-07-09

申请号：US15795595

申请日：2017-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo-Min Sohn ,  Ho-Young Song ,  Sang-Joon Hwang ,  Cheol Kim ,  Dong-Hyun Sohn

IPC: G11C29/44 ,  G11C29/56 ,  G11B20/18 ,  G01R31/3187 ,  G06F11/27 ,  G06F11/20 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C17/18 ,  G11C29/02 ,  G11C29/00 ,  G11C8/06 ,  G11C8/10 ,  G11C11/4078 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/36 ,  G11C29/42

Abstract: Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

公开(公告)号：US09165673B2

公开(公告)日：2015-10-20

申请号：US13795567

申请日：2013-03-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Yu ,  Ho-Young Song ,  Sung-Min Seo ,  Sang-Joon Hwang

IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

CPC classification number: G11C17/00 ,  G11C17/16 ,  G11C17/18

Abstract: A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Abstract translation: 半导体存储器件包括：存储单元阵列，被配置为存储包括验证码的数据; 感测单元，被配置为感测存储的包括验证码的数据; 以及验证单元，被配置为基于感测条件来确定所述感测单元是否能够感测所存储的数据，其中所述验证单元被配置为基于所述感测条件来确定所述感测单元是否能够感测所存储的数据，以及 由感测单元感测的验证码的值。

公开(公告)号：US09858981B2

公开(公告)日：2018-01-02

申请号：US15372750

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC: G11C17/00 ,  G11C11/406 ,  G11C17/16 ,  G11C11/408 ,  G11C29/44

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.