公开(公告)号：US09524770B2

公开(公告)日：2016-12-20

申请号：US15142491

申请日：2016-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC: G11C7/00 ,  G11C11/406 ,  G11C17/16 ,  G11C29/44 ,  G11C11/408

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

公开(公告)号：US09858981B2

公开(公告)日：2018-01-02

申请号：US15372750

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Young Lee ,  Kyo-Min Sohn ,  Sang-Joon Hwang ,  Sung-Min Seo ,  Sang-Bo Lee ,  Nak-Won Heo

IPC: G11C17/00 ,  G11C11/406 ,  G11C17/16 ,  G11C11/408 ,  G11C29/44

CPC classification number: G11C11/40615 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C29/44 ,  G11C29/783 ,  G11C29/785 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.