公开(公告)号：US10229900B2

公开(公告)日：2019-03-12

申请号：US15693707

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Wan Kim ,  Sung-Chul Park ,  Won-Il Bae

IPC: G11C5/02 ,  H01L25/18 ,  H01L25/065 ,  G11C7/10 ,  G11C5/04 ,  G11C5/06

Abstract: A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.

公开(公告)号：US09171605B1

公开(公告)日：2015-10-27

申请号：US14103794

申请日：2013-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Sik Kim ,  Won-Il Bae ,  Myeong-O Kim ,  Min-Soo Kim ,  Ho-Seok Seol ,  Min-Sang Park ,  Kyo-Min Sohn ,  Chi-Hwan Lee ,  Sang-Joon Hwang

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/40607 ,  G06F12/1018 ,  G11C7/00 ,  G11C11/402 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/408

Abstract: Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Abstract translation: 提供了使用n位地址来检测半导体器件的集中地址的方法。 该方法包括：对于k组中的每一组，将n位地址划分为k个组，其中n和k中的每一个是等于或大于2的整数，检测对应于该组的一个或多个集中子地址，以及 通过组合用于k个组的一个或多个集中子地址来生成至少一个集中地址。

公开(公告)号：US10423483B2

公开(公告)日：2019-09-24

申请号：US15348315

申请日：2016-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won-Il Bae

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C29/00 ,  G11C29/04

Abstract: A method of operating a semiconductor memory device including a memory cell array and an error correction circuit is provided as follows. A write command, main data and an address are received from a memory controller. An error correction data unit is provided to the error correction circuit. The error correction data unit includes the main data. At least one parity bit is generated based on the error correction data unit. A write operation is performed, in response to the write command, on a target page selected by the address so that the at least one parity bit and the main data are written to the target page and the at least one parity data is written later than the main data to the target page.

公开(公告)号：US20180158809A1

公开(公告)日：2018-06-07

申请号：US15693707

申请日：2017-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Wan Kim ,  Sung-Chul Park ,  Won-Il Bae

IPC: H01L25/18 ,  H01L25/065 ,  G11C7/10

CPC classification number: H01L25/18 ,  G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1006 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.

公开(公告)号：US09589674B2

公开(公告)日：2017-03-07

申请号：US14305095

申请日：2014-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Pil Son ,  Young-Soo Sohn ,  Uk-Song Kang ,  Chul-Woo Park ,  Jung-Hwan Choi ,  Won-Il Bae ,  Kyo-Min Sohn

IPC: G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1048 ,  G11C2029/0411

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract translation: 在操作存储器件的方法中，接收来自存储器控制器的命令和第一地址。 从存储器件的存储单元阵列读取包括对应于第一地址的第一组数据，对应于第二地址的第二组数据和读取奇偶校验数据的读码字。 通过使用基于读取的线字的ECC电路的操作错误检查和校正（ECC）来生成校正的数据。