公开(公告)号：US11887672B2

公开(公告)日：2024-01-30

申请号：US17693013

申请日：2022-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-Woo Lee ,  Seungyeon Kim ,  Dongha Shin ,  Beakhyung Cho

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/30 ,  G11C16/28 ,  G11C7/10

CPC classification number: G11C16/16 ,  G11C7/1039 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A nonvolatile memory device includes a plurality of bit lines that is connected with a plurality of cell strings, a common source line that is connected with the plurality of cell strings, at least one dummy bit line that is provided between the common source line and the plurality of bit lines, a control logic circuit that generates at least one dummy bit line driving signal in response to a command from an external device, and a dummy bit line driver that selectively provides a first voltage to the at least one dummy bit line in response to the dummy bit line driving signal.

公开(公告)号：US20230387105A1

公开(公告)日：2023-11-30

申请号：US18447367

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Yu-Tso Lin ,  Chih-Hsien Chang ,  Min-Shueh Yuan ,  Robert Bogdan Staszewski ,  Seyednaser Pourmousavian

IPC: H01L27/06 ,  G11C16/30 ,  H01L29/94 ,  H01L27/07

CPC classification number: H01L27/0629 ,  G11C16/30 ,  H02M3/07 ,  H01L27/0788 ,  H01L29/94

Abstract: A device includes a capacitive element that is coupled between first and second nodes and that includes a first well region, a second well region, and a transistor. The second well region is formed in the first well region, has a different conductivity type than the first well region, and is coupled to the second node. The transistor includes source and drain regions formed in the second well region and coupled to each other and to the second node, a channel region between the source and drain regions, and a gate region over the channel region. The first well region and the gate region are coupled to each other and to the first node, whereby a capacitance of the capacitive element is increased without substantially enlarging a physical size of the capacitive element.

公开(公告)号：US11830558B2

公开(公告)日：2023-11-28

申请号：US17742142

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwon Shim ,  Sangwon Park ,  Bongsoon Lim ,  Yoonhee Choi

IPC: G11C16/30 ,  G11C5/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/30 ,  G11C5/14 ,  H01L24/05 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05147 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells and a first peripheral circuit disposed below the first memory cell array; a second memory area including a second memory cell array having a plurality of second memory cells and a second peripheral circuit disposed below the second memory cell array; and a pad area including a power wiring. The first and second memory areas respectively include first and second local lockout circuits separately determining whether to lock out of each of the memory areas. The first and second memory areas are included in a single semiconductor chip to share the pad area, and the first and second memory areas operate individually. Accordingly, in the memory device, unnecessary data loss may be reduced by selectively stopping an operation of only a memory area requiring recovery.

公开(公告)号：US11830553B2

公开(公告)日：2023-11-28

申请号：US17412363

申请日：2021-08-26

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Cheng-Jer Yang

IPC: G11C16/08 ,  H03K3/015 ,  G11C16/30 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0433 ,  G11C16/30 ,  H03K3/015

Abstract: The application provides a Word Line (WL) drive circuit and a Dynamic Random Access Memory (DRAM). The WL drive circuit includes a first transistor, a second transistor, a third transistor and a fourth transistor. A gate of the first transistor is connected to a WL switch-off voltage, a drain is connected to the WL; a gate of the second transistor is connected to a first drive voltage of the WL, a drain is connected to the WL; and a source of the first transistor and a source of the second transistor are both connected to a negative bias through the third transistor.

公开(公告)号：US11823722B2

公开(公告)日：2023-11-21

申请号：US18110008

申请日：2023-02-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Mustafa N Kaynak ,  Sampath K Ratnam ,  Shane Nowell ,  Peter Feeley ,  Sivagnanam Parthasarathy

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/32 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A processing device of a memory sub-system is configured to identify a read level of a plurality of read levels associated with a voltage bin of a plurality of voltage bins of a memory device; assign a first threshold voltage offset to the read level of the voltage bin; assign a second threshold voltage offset to the read level of the voltage bin; perform, on block associated with the read level, a first operation of a first operation type using the first threshold voltage offset; and perform, on the blocks associated with the read level, a second operation of a second operation type using the second threshold voltage offset.

公开(公告)号：US20230368848A1

公开(公告)日：2023-11-16

申请号：US18348570

申请日：2023-07-07

Applicant: Kioxia Corporation

Inventor： Takeshi HIOKA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

公开(公告)号：US11817157B2

公开(公告)日：2023-11-14

申请号：US17346880

申请日：2021-06-14

Applicant: SanDisk Technologies LLC

Inventor： Ming Wang ,  Liang Li ,  Shih-Chung Lee

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: The storage device that includes a non-volatile memory with a control circuitry that is communicatively coupled to an array of memory cells that are arranged in a plurality of word lines. The control circuitry is configured to program the memory cells in a plurality of programming loops. The programming loops include applying a programming pulse to a selected word line of the plurality of word lines. The programming loops also include applying a verify pulse VN to the selected word line to simultaneously verify a lower tail of the memory cells being programmed to a data state N and an upper tail of the memory cells that have been programmed to a data state N−1. The data state N−1 has a lower voltage threshold than the data state N.

公开(公告)号：US11810620B2

公开(公告)日：2023-11-07

申请号：US17458067

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Takenaka ,  Akihiko Chiba ,  Teppei Higashitsuji ,  Kiyofumi Sakurai ,  Hiroaki Nakasa ,  Youichi Magome

IPC: G11C8/12 ,  G11C16/14 ,  G11C5/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

公开(公告)号：US20230352099A1

公开(公告)日：2023-11-02

申请号：US18184893

申请日：2023-03-16

Applicant: KIOXIA CORPORATION

Inventor： Koji KATO ,  Yuki SHIMIZU ,  Shuhei OKETA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L23/528 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  H01L23/5283 ,  G11C16/10 ,  G11C16/32 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

公开(公告)号：US20230343399A1

公开(公告)日：2023-10-26

申请号：US17725109

申请日：2022-04-20

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Ning Zhang ,  Ruxin Wei ,  Yongyong Wang ,  Wei Huang

IPC: G11C16/30 ,  G11C16/04 ,  G05F1/567

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G05F1/567 ,  H03K19/20

Abstract: A voltage supply circuit includes a temperature compensation circuit and a voltage regulation circuit. The temperature compensation circuit includes a comparator circuit comparing a device temperature value with a reference value to output a comparison result, and a compensation controller circuit receiving the comparison result, a compensation value control signal, and a compensation enable signal, and outputting a voltage control signal according to the comparison result. The voltage regulation circuit receives the voltage control signal and provides a voltage output according to the control signal.