公开(公告)号：US11171091B2

公开(公告)日：2021-11-09

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US20210125927A1

公开(公告)日：2021-04-29

申请号：US16695028

申请日：2019-11-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Li-Hsuan Ho ,  Tsuo-Wen Lu ,  Shih-Hao Liang ,  Tsung-Hsun Wu ,  Po-Jen Chuang ,  Chi-Mao Hsu

IPC: H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L29/49 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238

Abstract: A semiconductor device includes a substrate having a NMOS region and a PMOS region; a gate structure extending along a first direction from the NMOS region to the PMOS region on the substrate; and a first contact plug landing directly on the gate structure closer to the PMOS region from a boundary separating the NMOS region and the PMOS region. Preferably, the semiconductor device further includes a first source/drain region extending along a second direction adjacent to two sides of the gate structure on the NMOS region and a second source/drain region extending along the second direction adjacent to two sides of the gate structure on the PMOS region.

公开(公告)号：US10910277B2

公开(公告)日：2021-02-02

申请号：US16802463

申请日：2020-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Jung Chuang ,  Po-Jen Chuang ,  Yu-Ren Wang ,  Chi-Mao Hsu ,  Chia-Ming Kuo ,  Guan-Wei Huang ,  Chun-Hsien Lin

IPC: H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

公开(公告)号：US20200266199A1

公开(公告)日：2020-08-20

申请号：US16866573

申请日：2020-05-05

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chih-Chieh Tsai ,  Pin-Hong Chen ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Shih-Fang Tzou

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor device for preventing row hammering issue in DRAM cell, including the steps of providing a substrate, forming a trench in the substrate, forming a gate dielectric conformally on the trench, forming an n-type work function metal layer conformally on the substrate and the gate dielectric, forming a titanium nitride layer conformally on the n-type work function metal layer, and filling a buried word line in the trench.

公开(公告)号：US10475799B2

公开(公告)日：2019-11-12

申请号：US15901875

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

公开(公告)号：US20190237468A1

公开(公告)日：2019-08-01

申请号：US15901875

申请日：2018-02-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Yi-Wei Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/108

Abstract: A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

公开(公告)号：US10217750B1

公开(公告)日：2019-02-26

申请号：US15712133

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Ger-Pin Lin ,  Kuan-Chun Lin ,  Chi-Mao Hsu ,  Shu-Yen Chan ,  Shih-Fang Tzou ,  Tsuo-Wen Lu ,  Tien-Chen Chan ,  Feng-Yi Chang ,  Shih-Kuei Yen ,  Fu-Che Lee

IPC: H01L27/108 ,  H01L21/28

Abstract: A method of fabricating a buried word line structure includes providing a substrate with a word line trench therein. Two source/drain doped regions are disposed in the substrate at two sides of the word line trench. Later, a silicon oxide layer is formed to cover the word line trench. A titanium nitride layer is formed to cover the silicon oxide layer. Next, a tilt ion implantation process is performed to implant silicon atoms into the titanium nitride layer to transform part of the titanium nitride layer into a titanium silicon nitride layer. A conductive layer is formed in the word line trench. Subsequently, part of the conductive layer, part of the titanium silicon nitride layer and part of the silicon oxide layer are removed to form a recess. Finally, a cap layer fills in the recess.

公开(公告)号：US09985110B2

公开(公告)日：2018-05-29

申请号：US15656778

申请日：2017-07-21

Applicant: United Microelectronics Corp.

Inventor： Pin-Hong Chen ,  Kuo-Chih Lai ,  Chia-Chang Hsu ,  Chun-Chieh Chiu ,  Li-Han Chen ,  Min-Chuan Tsai ,  Kuo-Chin Hung ,  Wei-Chuan Tsai ,  Hsin-Fu Huang ,  Chi-Mao Hsu

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L29/267 ,  H01L29/78 ,  H01L21/285

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L29/267 ,  H01L29/45 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide layer is formed directly on the SiP epitaxial layer and thus prevents oxidation of the SiP epitaxial layer. A contact plug is formed over the crystalline metal silicide layer.

公开(公告)号：US09659937B2

公开(公告)日：2017-05-23

申请号：US14683128

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yun Chang ,  Chi-Mao Hsu ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

公开(公告)号：US09653300B2

公开(公告)日：2017-05-16

申请号：US13864218

申请日：2013-04-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Nien-Ting Ho ,  Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Wei-Yu Chen ,  Min-Chuan Tsai ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L27/148 ,  H01L21/28 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/28088 ,  H01L21/823842 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7843 ,  H01L29/7848

Abstract: A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.