公开(公告)号：US20220367399A1

公开(公告)日：2022-11-17

申请号：US17411701

申请日：2021-08-25

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Meng-Liang LIN ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

摘要： A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.

公开(公告)号：US20220359465A1

公开(公告)日：2022-11-10

申请号：US17395946

申请日：2021-08-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Hua WANG ,  Shu-Shen YEH ,  Yu-Sheng LIN ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L21/48

摘要： A package structure is provided. The package structure includes a first package component, a second package component, and a lid structure. The first package component includes a plurality of integrated circuit dies and an underfill formed between the integrated circuit dies. The second package component includes a substrate, and the first package component is mounted on the substrate. The lid structure is disposed on the second package component and around the first package component, and the lid structure covers the integrated circuit dies and exposes the underfill.

公开(公告)号：US20210384125A1

公开(公告)日：2021-12-09

申请号：US17405389

申请日：2021-08-18

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Techi WONG ,  Meng-Liang LIN ,  Yi-Wen WU ,  Po-Yao CHUANG ,  Shin-Puu JENG

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07

摘要： A method for forming a package structure is provided. The method includes forming a first interconnect structure over a carrier substrate and disposing a first die structure over the first interconnect structure. The method includes forming a dam structure over the first die structure. The method also includes forming a protection layer over a second interconnect structure. The method further includes bonding the second interconnect structure over the dam structure. In addition, the method includes forming a package layer between the first interconnect structure and the second interconnect structure. The method also includes removing the protection layer.

公开(公告)号：US20210335728A1

公开(公告)日：2021-10-28

申请号：US17366413

申请日：2021-07-02

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsiao-Wen LEE ,  Hsien-Wen LIU ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/304 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L21/02 ,  H01L21/48

摘要： Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

公开(公告)号：US20210242122A1

公开(公告)日：2021-08-05

申请号：US17233852

申请日：2021-04-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Po-Hao TSAI ,  Po-Yao CHUANG ,  Feng-Cheng HSU ,  Shuo-Mao CHEN ,  Techi WONG

IPC分类号： H01L23/498 ,  H01L25/10 ,  H01L21/52 ,  H01L23/053 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L25/00

摘要： A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

公开(公告)号：US20170229534A1

公开(公告)日：2017-08-10

申请号：US15497594

申请日：2017-04-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun Hua CHANG ,  Der-Chyang YEH ,  Kuang-Wei CHENG ,  Yuan-Hung LIU ,  Shang-Yun HOU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

IPC分类号： H01L49/02 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L28/60 ,  H01L21/02 ,  H01L21/768 ,  H01L21/76832 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53295 ,  H01L28/40 ,  H01L29/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device includes forming a through via extending into a substrate. The method further includes forming a first insulating layer over the surface of the substrate. The method further includes forming a first metallization layer in the first insulating layer and electrically connected to the through via. The method further includes forming a capacitor over the first metallization layer, wherein the capacitor comprises a first capacitor dielectric layer and a second capacitor dielectric layer. The method further includes depositing a continuous second insulating layer over the first insulating layer. The capacitor is within the second insulating layer. The method further includes depositing a third insulating layer over the second insulating layer. The method further includes forming a second metallization layer in the third insulating layer. A bottom surface of the second metallization layer is below a bottom surface of the third insulating layer.

公开(公告)号：US20150037960A1

公开(公告)日：2015-02-05

申请号：US14515368

申请日：2014-10-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chun Hua CHANG ,  Der-Chyang YEH ,  Kuang-Wei CHENG ,  Yuan-Hung LIU ,  Shang-Yun HOU ,  Wen-Chih CHIOU ,  Shin-Puu JENG

IPC分类号： H01L49/02 ,  H01L21/768

CPC分类号： H01L28/40 ,  H01L21/02 ,  H01L21/768 ,  H01L23/147 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/53295 ,  H01L28/60 ,  H01L29/02 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.

摘要翻译： 形成器件的方法包括形成从衬底的表面延伸到衬底中的通孔。 该方法还包括在衬底的表面上形成第一绝缘层。 该方法还包括在第一绝缘层中形成第一金属化层，第一金属化层电连接通孔。 该方法还包括在第一金属化层上形成电容器。 电容器包括在第一金属化层上的第一电容器电介质层和在第一电容器介电层上的第二电容器介电层。 该方法还包括在电容器上形成第二金属化层并电连接电容器。

公开(公告)号：US20240312798A1

公开(公告)日：2024-09-19

申请号：US18675560

申请日：2024-05-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng LIN ,  Shu-Shen YEH ,  Chin-Hua WANG ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L25/065

CPC分类号： H01L21/563 ,  H01L21/565 ,  H01L23/3142 ,  H01L23/49838 ,  H01L23/585 ,  H01L24/05 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/04105

摘要： A semiconductor die package is provided, including a package substrate, and two semiconductor dies disposed over the package substrate and arranged in a first direction. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. The ring structure includes a first part having a first height and a second part recessed from the bottom surface and having a second height lower than the first height. The first part includes multiple higher parts arranged side by side in at least some of side areas of the ring structure, and the second part includes multiple lower parts between the higher parts. The lower parts include multiple first lower parts arranged in multiple corner areas of the ring structure and multiple second lower parts arranged in opposite side areas of the ring structure extending in the first direction.

公开(公告)号：US20240297089A1

公开(公告)日：2024-09-05

申请号：US18662075

申请日：2024-05-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Ming-Chih YEW ,  Li-Ling LIAO ,  Chin-Hua WANG ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3178 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/73204 ,  H01L2924/1434 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182

摘要： A package structure is provided. The package structure includes a package component over a redistribution structure, a substrate under the redistribution structure, and an underfill material over the redistribution structure and including a first extending portion in the structure. The package component has a first sidewall and a second sidewall connected to the first sidewall at a first corner. In a plan view, the first extending portion has a first sidewall passing through the first sidewall of the package component and a second sidewall opposite to the first sidewall of the first extending portion and passing through the second sidewall of the package component.

公开(公告)号：US20240243076A1

公开(公告)日：2024-07-18

申请号：US18428245

申请日：2024-01-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Shen YEH ,  Chin-Hua WANG ,  Po-Chen LAI ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L21/52 ,  H01L23/053 ,  H01L23/16

CPC分类号： H01L23/562 ,  H01L21/52 ,  H01L23/053 ,  H01L23/16

摘要： A semiconductor device package is provided, including a substrate, a semiconductor device, a ring structure, a lid structure, and at least one adhesive member. The semiconductor device is disposed over the substrate. The ring structure is disposed over the substrate and surrounds the semiconductor device. The ring structure comprises a first ring part and a second ring part on opposite sides of the semiconductor device. A first gap is formed between the first ring part and the semiconductor device, a second gap is formed between the second ring part and the semiconductor device, and the first gap is smaller than the second gap. The lid structure is disposed over the ring structure and extends across the semiconductor device. The adhesive member is disposed in the first gap and configured to connect the lid structure and the first surface of the substrate.