公开(公告)号：US20200251571A1

公开(公告)日：2020-08-06

申请号：US16690005

申请日：2019-11-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung TSAI ,  Clement Hsingjen WANN ,  Kuo-Feng YU ,  Ming-Hsi YEH ,  Shahaji B. MORE ,  Yu-Ming LIN

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234

Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

公开(公告)号：US20200044085A1

公开(公告)日：2020-02-06

申请号：US16586126

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Carlos H. DIAZ ,  Chun Hsiung TSAI ,  Yu-Ming LIN

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L29/08 ,  H01L29/36

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.

公开(公告)号：US20190252250A1

公开(公告)日：2019-08-15

申请号：US16390097

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wai-Yi LIEN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L23/535 ,  H01L29/78 ,  H01L29/739

CPC classification number: H01L29/4983 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7391 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain over the semiconductor substrate, a bottom conductive feature over the source/drain, a gate structure over the semiconductor substrate, a first spacer between the gate structure and the bottom conductive feature, a second spacer over the first spacer, and a contact plug landing on the bottom conductive feature and the second spacer. A top surface of the gate structure is free from coverage by the second spacer.

公开(公告)号：US20190148499A1

公开(公告)日：2019-05-16

申请号：US15959411

申请日：2018-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. ,  NATIONAL TAIWAN UNIVERSITY

Inventor： Yu-Ming LIN ,  Chao-Hsin WU ,  Hsun-Ming CHANG ,  Samuel C. PAN

IPC: H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/385

Abstract: A method includes providing a black phosphorus (BP) layer over a substrate, forming a dopant source layer over the BP layer, annealing the dopant source layer to drive a dopant from the dopant source layer into the BP layer, and forming a conductive contact over the dopant source layer.

公开(公告)号：US20190140062A1

公开(公告)日：2019-05-09

申请号：US16222073

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Wai-Yi LIEN ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A FinFET device structure is provided. The FinFET device structure includes a first gate structure formed over a fin structure and a first spacer layer formed on the first gate structure. The FinFET device structure includes a first insulation layer formed over the fin structure, and the first insulating layer is adjacent to and separated from the first spacer layer. The FinFET device structure includes a conductive plug formed over the first gate structure, and the conductive plug is formed over the first spacer layer and the first insulation layer.

公开(公告)号：US20190097051A1

公开(公告)日：2019-03-28

申请号：US15893081

申请日：2018-02-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsiung TSAI ,  Shahaji B. MORE ,  Cheng-Yi PENG ,  Yu-Ming LIN ,  Kuo-Feng YU ,  Ziwei FANG

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/45 ,  H01L29/165 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/06

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure extended above a substrate and a gate structure formed over a middle portion of the fin structure. The middle portion of the fin structure is wrapped by the gate structure. The FinFET device structure includes a source/drain (S/D) structure adjacent to the gate structure, and the S/D structure includes a doped region at an outer portion of the S/D structure, and the doped region includes gallium (Ga). The FinFET device structure includes a metal silicide layer formed over the doped region of the S/D structure, and the metal silicide layer is in direct contact with the doped region of the S/D structure.

公开(公告)号：US20190013396A1

公开(公告)日：2019-01-10

申请号：US16104372

申请日：2018-08-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Hao WANG ,  Wai-Yi LIEN ,  Gwan-Sin CHANG ,  Yu-Ming LIN ,  Ching HSUEH ,  Jia-Chuan YOU ,  Chia-Hao CHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/8238

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor fin, a first gate stack, and a first metal element-containing dielectric mask. The semiconductor fin protrudes from the substrate. The first gate stack is over the semiconductor fin. The first metal element-containing dielectric mask is over the first gate stack.

公开(公告)号：US20180175213A1

公开(公告)日：2018-06-21

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256

CPC classification number: H01L29/78696 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/823821 ,  H01L21/8256 ,  H01L27/0886 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/7851

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US20180151751A1

公开(公告)日：2018-05-31

申请号：US15401463

申请日：2017-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ling-Yen YEH ,  Chih-Sheng CHANG ,  Wilman TSAI ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L29/40 ,  H01L29/06 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/24 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L21/0228 ,  H01L21/02527 ,  H01L21/02565 ,  H01L21/02568 ,  H01L21/31116 ,  H01L27/04 ,  H01L29/0653 ,  H01L29/1606 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/401 ,  H01L29/66045 ,  H01L29/66522 ,  H01L29/66969 ,  H01L29/778

Abstract: A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.

公开(公告)号：US20180151700A1

公开(公告)日：2018-05-31

申请号：US15429335

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ming LIN ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/10 ,  H01L29/24 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/1037 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure.