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    INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES
    1.
    发明申请
    INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES 审中-公开

    公开(公告)号：US20190115341A1

    公开(公告)日：2019-04-18

    申请号：US16228985

    申请日：2018-12-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Tang LIN ,  Clement Hsingjen WANN ,  Neng-Kuo CHEN

    IPC: H01L27/06 ,  H01L23/522 ,  H01L27/088

    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

    METHOD FOR REMOVING HARD MASK OXIDE AND MAKING GATE STRUCTURE OF SEMICONDUCTOR DEVICES
    2.
    发明申请
    METHOD FOR REMOVING HARD MASK OXIDE AND MAKING GATE STRUCTURE OF SEMICONDUCTOR DEVICES 有权
    用于去除硬掩模氧化物和制造半导体器件的门结构的方法

    公开(公告)号：US20140162446A1

    公开(公告)日：2014-06-12

    申请号：US13707769

    申请日：2012-12-07

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-An LIN ,  Chun-Wei CHANG ,  Neng-Kuo CHEN ,  Sey-Ping SUN ,  Clement Hsingjen WANN

    IPC: H01L29/40

    CPC classification number: H01L21/823437

    Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.

    Abstract translation: 一种方法包括在半导体衬底上形成第一栅极，在第一栅极上形成硬掩模，以及在硬掩模上形成接触蚀刻停止层（CESL）。 在形成硬掩模的步骤和形成CESL的步骤之间没有去除硬掩模。 该方法还包括在CESL上形成层间电介质层（ILD）层，以及执行一个或多个CMP工艺以使ILD层平坦化，去除硬掩模上的CESL，以及去除硬掩模的至少一部分。

    REPLACEMENT CHANNELS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME USING DOPANT CONCENTRATION BOOST
    5.
    发明申请
    REPLACEMENT CHANNELS FOR SEMICONDUCTOR DEVICES AND METHODS FOR FORMING THE SAME USING DOPANT CONCENTRATION BOOST 有权
    用于半导体器件的替换通道及其使用浓度浓度增加的方法

    公开(公告)号：US20140084351A1

    公开(公告)日：2014-03-27

    申请号：US13628359

    申请日：2012-09-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yu-Lien HUANG ,  Ming-Huan TSAI ,  Clement Hsingjen WANN

    IPC: H01L29/78 ,  H01L21/26 ,  H01L21/425

    CPC classification number: H01L29/7851 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66651

    Abstract: A replacement channel and a method for forming the same in a semiconductor device are provided. A channel area is defined in a substrate which is a surface of a semiconductor wafer or a structure such as a fin formed over the wafer. Portions of the channel region are removed and are replaced with a replacement channel material formed by an epitaxial growth/deposition process to include a first dopant concentration level less than a first dopant concentration level. A subsequent doping operation or operations is then used to boost the average dopant concentration to a level greater than the first dopant concentration level. The replacement channel material is formed to include a gradient in which the upper portion of the replacement channel material has a greater dopant concentration than the lower portion of replacement channel material.

    Abstract translation: 提供了一种替代通道​​及其在半导体器件中的形成方法。 沟道区域被限定在衬底中，该衬底是半导体晶片的表面或在晶片上形成的诸如鳍片的结构。 沟道区域的部分被去除，并被用外延生长/沉积工艺形成的替代沟道材料代替以包括小于第一掺杂剂浓度水平的第一掺杂剂浓度水平。 然后使用随后的掺杂操作或操作来将平均掺杂剂浓度升高到大于第一掺杂剂浓度水平的水平。 替换通道材料形成为包括其中更换通道材料的上部具有比替换通道材料的下部更大的掺杂剂浓度的梯度。

    INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES
    6.
    发明申请
    INTER-LEVEL CONNECTION FOR MULTI-LAYER STRUCTURES 有权

    公开(公告)号：US20210257356A1

    公开(公告)日：2021-08-19

    申请号：US17135778

    申请日：2020-12-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Tang LIN ,  Clement Hsingjen WANN ,  Neng-Kuo CHEN

    IPC: H01L27/06 ,  H01L27/088 ,  H01L23/522

    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

    GATE SPACER STRUCTURES AND METHODS FOR FORMING THE SAME
    10.
    发明申请
    GATE SPACER STRUCTURES AND METHODS FOR FORMING THE SAME 审中-公开

    公开(公告)号：US20200251571A1

    公开(公告)日：2020-08-06

    申请号：US16690005

    申请日：2019-11-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun Hsiung TSAI ,  Clement Hsingjen WANN ,  Kuo-Feng YU ,  Ming-Hsi YEH ,  Shahaji B. MORE ,  Yu-Ming LIN

    IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234

    Abstract: The present disclosure relates to a semiconductor device including a substrate having a top surface and a gate stack. The gate stack includes a gate dielectric layer on the substrate and a gate electrode on the gate dielectric layer. The semiconductor device also includes a multi-spacer structure. The multi-spacer includes a first spacer formed on a sidewall of the gate stack, a second spacer, and a third spacer. The second spacer includes a first portion formed on a sidewall of the first spacer and a second portion formed on the top surface of the substrate. The second portion of the second spacer has a thickness in a first direction that gradually decreases. The third spacer is formed on the second portion of the second spacer and on the top surface of the substrate. The semiconductor device further includes a source/drain region formed in the substrate, and a portion of the third spacer abuts the source/drain region and the second portion of the second spacer.

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