公开(公告)号：US12112829B2

公开(公告)日：2024-10-08

申请号：US17575397

申请日：2022-01-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Ying Lee ,  Chia-En Huang ,  Meng-Sheng Chang

IPC: G11C7/14 ,  G11C7/18 ,  H01L25/065 ,  H10B12/00

CPC classification number: G11C7/14 ,  G11C7/18 ,  H01L25/0655 ,  H10B12/056 ,  H10B12/36

Abstract: A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.

公开(公告)号：US20240315014A1

公开(公告)日：2024-09-19

申请号：US18670472

申请日：2024-05-21

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yih Wang

IPC: H10B20/20 ,  H01L23/525 ,  H10B20/25

CPC classification number: H10B20/20 ,  H01L23/5256 ,  H10B20/25

Abstract: A memory device is disclosed. The memory device includes a plurality of one-time programmable (OTP) memory cells. Each OTP memory cell includes a transistor disposed on a first side of a substrate, and a capacitor disposed on a second side of the substrate opposite to the first side and electrically connected to the transistor. The capacitor includes a first terminal, a second terminal formed vertically lower than the first terminal, and an insulation layer vertically interposed therebetween.

公开(公告)号：US12089402B2

公开(公告)日：2024-09-10

申请号：US18346700

申请日：2023-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng Chang ,  Chien-Ying Chen ,  Chia-En Huang ,  Yih Wang

IPC: H10B20/20 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B20/20 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/528

Abstract: A method of generating an IC layout diagram includes abutting first and second cells to define a first active region including first and second anti-fuse bits, abutting third and fourth cells to define a second active region including third and fourth anti-fuse bits, and defining a third active region including fifth and sixth anti-fuse bits adjacent to the first through fourth anti-fuse bits. The first cell includes first and second via regions overlapping first and second gate regions shared by respective structures and transistors of the first, third, and fifth anti-fuse bits, the fourth cell includes third and fourth via regions overlapping third and fourth gate regions shared by respective transistors and structures of the second, fourth, and sixth anti-fuse bits, the third cell includes fifth and sixth via regions overlapping the first gate region, and the second cell includes seventh and eighth via regions overlapping the fourth gate region.

公开(公告)号：US20240274189A1

公开(公告)日：2024-08-15

申请号：US18628284

申请日：2024-04-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yih Wang

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/004 ,  G11C2213/74 ,  G11C2213/79

Abstract: A memory device includes at least a non-volatile memory cell. The non-volatile memory cell includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled in series. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage that is different from the first threshold voltage. The first and the second transistors have their channels doped in respective different concentrations.

公开(公告)号：US12052859B2

公开(公告)日：2024-07-30

申请号：US18066290

申请日：2022-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yao-Jen Yang ,  Yih Wang

IPC: H10B20/20 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H10B99/00 ,  G06F12/14

CPC classification number: H10B20/20 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42316 ,  H01L29/7851 ,  H10B99/00 ,  G06F12/1433

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

公开(公告)号：US12027221B2

公开(公告)日：2024-07-02

申请号：US17815141

申请日：2022-07-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Sheng Chang ,  Yao-Jen Yang

IPC: G11C17/18 ,  G11C17/16 ,  H10B20/20

CPC classification number: G11C17/18 ,  G11C17/16 ,  H10B20/20

Abstract: An integrated circuit (IC) device includes a first active region extending along a first direction, a first pair of gate regions extending across the first active region along a second direction transverse to the first direction, and a first metal layer. The first pair of gate regions and the first active region configure a first program transistor and a first read transistor sharing a common source/drain region. The first metal layer includes a first program word line pattern over and coupled to the gate region of the first program transistor, a first read word line pattern over and coupled to the gate region of the first read transistor, a first source line pattern coupled to another source/drain region of the first program transistor, and a first bit line pattern coupled to another source/drain region of the first read transistor.

公开(公告)号：US12027204B2

公开(公告)日：2024-07-02

申请号：US18357785

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang ,  Yi-Ching Liu ,  Yih Wang

IPC: G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

公开(公告)号：US12002802B2

公开(公告)日：2024-06-04

申请号：US18158452

申请日：2023-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Meng-Han Lin ,  Meng-Sheng Chang

IPC: H01L29/40 ,  H01L21/82 ,  H01L27/02

CPC classification number: H01L27/0288 ,  H01L21/82 ,  H01L27/0218

Abstract: An integrated circuit (IC) structure includes a semiconductor substrate, a shallow trench isolation (STI) region, and a capacitor. The STI region is embedded in the semiconductor substrate. The capacitor includes first and second conductive stacks. The first conductive stack includes a first dummy gate strip disposed entirely within the STI region and a plurality of first metal dummy gate contacts landing on the first metal capacitor strip. The second conductive stack includes a second dummy gate strip disposed entirely within the STI region and extending in parallel with the first dummy gate strip, and a plurality of second dummy gate contacts landing on the second dummy gate strip, wherein the first conductive stack is electrically isolated from the second conductive stack.

公开(公告)号：US11963348B2

公开(公告)日：2024-04-16

申请号：US17818954

申请日：2022-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Geng-Cing Lin ,  Ze-Sian Lu ,  Meng-Sheng Chang ,  Chia-En Huang ,  Jung-Ping Yang ,  Yen-Huei Chen

IPC: H10B20/00 ,  H01L21/265 ,  H01L23/528

CPC classification number: H10B20/34 ,  H01L21/26513 ,  H01L23/5286

Abstract: A method of making a ROM structure includes the operations of forming an active area having a channel, a source region, and a drain region; depositing a gate electrode over the channel; depositing a conductive line over at least one of the source region and the drain region; adding dopants to the source region and the drain region of the active area; forming contacts to the gate electrode, the source region, and the drain; depositing a power rail, a bit line, and at least one word line of the integrated circuit against the contacts; and dividing the active area with a trench isolation structure to electrically isolate the gate electrode from the source region and the drain region.

公开(公告)号：US11956947B2

公开(公告)日：2024-04-09

申请号：US17407281

申请日：2021-08-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Chia-En Huang

IPC: H10B20/20

CPC classification number: H10B20/20

Abstract: An OTP memory cell is provided. The OTP memory cell includes: an antifuse transistor, wherein a gate terminal of the antifuse transistor is connected to a first word line having a first signal, and the antifuse transistor is selectable between a first state and a second state in response to the first signal; and a selection transistor connected between the antifuse transistor and a bit line, wherein a gate terminal of the selection transistor is connected to a second word line having a second signal, and the selection transistor is configured to provide access to the antifuse transistor in response to the second signal. A first terminal of the antifuse transistor is a vacancy terminal, and a second terminal of the antifuse transistor is connected to the selection transistor.