公开(公告)号：US20210383867A1

公开(公告)日：2021-12-09

申请号：US17409341

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/419 ,  G11C11/16

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US20210272647A1

公开(公告)日：2021-09-02

申请号：US17130250

申请日：2020-12-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hiroki Noguchi ,  Ku-Feng Lin ,  Yih Wang

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/24 ,  G11C29/20

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells, the plurality of memory cells comprising a plurality of data memory cells including a first data memory cell and a plurality of backup memory cells including a first backup memory cell; a storage storing an error table configured to record errors in the plurality of data memory cells, the error table including a plurality of error table entries, each error table entry corresponding to one of the plurality of data memory cell and having an address and a failure count; and a controller configured to replace the first data memory cell with the first backup memory cell based on the error table.

公开(公告)号：US20210174854A1

公开(公告)日：2021-06-10

申请号：US16709622

申请日：2019-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Win-San Khwa ,  Hiroki Noguchi ,  Ku-Feng Lin

IPC: G11C11/16 ,  H03M7/16 ,  H03K19/20

Abstract: An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

公开(公告)号：US10372948B2

公开(公告)日：2019-08-06

申请号：US14969621

申请日：2015-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kai-Chun Lin ,  Ku-Feng Lin ,  Hung-Chang Yu ,  Yu-Der Chih

IPC: G06F21/79 ,  G06F12/14

Abstract: A memory device is provided which comprises a memory array, a first scrambling circuit and a second scrambling circuit. The first scrambling circuit is configured to provide first scrambled data with a first scrambling pattern in response to input data. The second scrambling circuit is configured to provide second scrambled data with a second scrambling pattern in response to the first scrambled data.

公开(公告)号：US20160072494A1

公开(公告)日：2016-03-10

申请号：US14942372

申请日：2015-11-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Hung-Chang Yu

IPC: H03K5/24

CPC classification number: H03K5/2481 ,  G11C7/062 ,  G11C13/004 ,  G11C2013/0054

Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.

Abstract translation: 提供具有减小的偏置钳位的感测电路和操作感测电路的方法。 感测电路可以包括参考路径和感测路径。 感测路径可以包括第一晶体管，钳位电容器和一对开关。 参考路径可以包括第二晶体管，钳位电容器和另一对开关。 接收偏置电压的公共增益级在充电模式下为相应路径的钳位电容器充电。 夹紧电容器可以在充电模式期间以串联或部分平行的方式充电。 每个路径可以耦合到比较器，比较器可以在感测模式期间感测路径之间的电流或电压变化。 感测电路可以被配置为提供以并行或串行方式感测多个感测和/或参考路径之间的电流或电压变化。

公开(公告)号：US20140266312A1

公开(公告)日：2014-09-18

申请号：US13906513

申请日：2013-05-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Hung-Chang Yu

IPC: H03K5/08 ,  H03K5/24

CPC classification number: H03K5/2481 ,  G11C7/062 ,  G11C13/004 ,  G11C2013/0054

Abstract: A sensing circuit having a reduced bias clamp and method of operating the sensing circuit are provided. The sensing circuit may include a reference path and a sensing path. The sensing path may include a first transistor, clamping capacitor and a pair of switches. The reference path may include a second transistor, clamping capacitor and another pair of switches. A common gain stage receiving a bias voltage charges the clamping capacitors for the respective paths in a charging mode. The clamping capacitors may be charged in a serial or partially parallel manner during the charging mode. Each path may be coupled to a comparator, which may sense current or voltage changes between the paths during a sense mode. The sensing circuit may be configured to provide for sensing current or voltage changes between multiple sensing and/or reference paths in a parallel or serial manner.

Abstract translation: 提供具有减小的偏置钳位的感测电路和操作感测电路的方法。 感测电路可以包括参考路径和感测路径。 感测路径可以包括第一晶体管，钳位电容器和一对开关。 参考路径可以包括第二晶体管，钳位电容器和另一对开关。 接收偏置电压的公共增益级在充电模式下为相应路径的钳位电容器充电。 夹紧电容器可以在充电模式期间以串联或部分平行的方式充电。 每个路径可以耦合到比较器，比较器可以在感测模式期间感测路径之间的电流或电压变化。 感测电路可以被配置为提供以并行或串行方式感测多个感测和/或参考路径之间的电流或电压变化。

公开(公告)号：US12277990B2

公开(公告)日：2025-04-15

申请号：US18677095

申请日：2024-05-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Sheng Chang ,  Ku-Feng Lin

IPC: G11C7/06 ,  G11C7/10 ,  G11C8/08

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

公开(公告)号：US12230352B2

公开(公告)日：2025-02-18

申请号：US18518578

申请日：2023-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin

IPC: G11C7/06

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

公开(公告)号：US12148487B2

公开(公告)日：2024-11-19

申请号：US17587242

申请日：2022-01-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ku-Feng Lin ,  Perng-Fei Yuh ,  Meng-Sheng Chang

IPC: G11C17/16

Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

公开(公告)号：US11903188B2

公开(公告)日：2024-02-13

申请号：US17673126

申请日：2022-02-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Meng-Sheng Chang ,  Jui-Che Tsai ,  Ku-Feng Lin ,  Yu-Wei Lin ,  Keh-Jeng Chang ,  Chansyun David Yang ,  Shao-Ting Wu ,  Shao-Yu Chou ,  Philex Ming-Yan Fan ,  Yoshitaka Yamauchi ,  Tzu-Hsien Yang

IPC: G11C17/16 ,  H10B20/20 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.