公开(公告)号：US20230369068A1

公开(公告)日：2023-11-16

申请号：US18361207

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng LIN ,  Po-Yao LIN ,  Shu-Shen YEH ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L23/367

CPC分类号： H01L21/4882 ,  H01L24/83 ,  H01L24/32 ,  H01L23/367 ,  H01L2224/3226 ,  H01L2224/838

摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over the wiring substrate. The chip package structure includes a first heat conductive structure over the chip package. The chip package structure includes a ring dam over the chip package and surrounding the first heat conductive structure. The ring dam has a gap. The chip package structure includes a heat dissipation lid over the first heat conductive structure and the ring dam.

公开(公告)号：US20230010707A1

公开(公告)日：2023-01-12

申请号：US17370299

申请日：2021-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Hua WANG ,  Kuang-Chun LEE ,  Shu-Shen YEH ,  Tsung-Yen LEE ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/373 ,  H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

摘要： Structures and formation methods of a chip package structure are provided. The chip package structure includes a semiconductor die bonded over an interposer substrate. The chip package structure also includes a warpage release layer structure. The warpage release layer structure includes an organic material layer and an overlying high coefficient of thermal expansion (CTE) material layer with a CTE that is substantially equal to or greater than 9 ppm/° C. The organic material layer is in direct contact with the upper surface of the semiconductor die, and the overlying high CTE material layer covers the upper surface of the semiconductor die.

公开(公告)号：US20220406752A1

公开(公告)日：2022-12-22

申请号：US17350371

申请日：2021-06-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Hua WANG ,  Shin-Puu JENG ,  Po-Yao LIN ,  Po-Chen LAI ,  Shu-Shen YEH ,  Ming-Chih YEW ,  Yu-Sheng LIN

IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/31 ,  H01L21/304 ,  H01L25/00

摘要： Structures and formation methods of a chip package structure are provided. The chip package structure includes adjacent first and second semiconductor dies bonded over an interposer substrate. The chip package structure also includes an insulating layer formed over the interposer substrate. The insulating layer has a first portion surrounding the first and second semiconductor dies and a second portion extending between a first sidewall of the first semiconductor die and a second sidewall of the second semiconductor die, and between the interposer substrate and the first and second semiconductor dies. The lateral distance from the top end of the first sidewall to the top end of the second sidewall is greater than the lateral distance from the bottom end of the first sidewall to the bottom end of the second sidewall.

公开(公告)号：US20220336359A1

公开(公告)日：2022-10-20

申请号：US17231310

申请日：2021-04-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Shu-Shen YEH ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L21/768

摘要： A semiconductor package structure includes a first bottom electrical connector, an interposer over the first bottom electrical connector, and a first top electrical connector over the first top via structures. The interposer includes first bottom via structures in contact with the first bottom electrical connector. The interposer also includes a first trace of a first redistribution layer structure over the first bottom via structures. The interposer also includes first via structures over the first redistribution layer. The interposer also includes a first trace of a second redistribution layer structure over the first via structures. The interposer also includes second via structures over the second redistribution layer structure. The first bottom via structures, the first via structures, and the second via structures are separated from each other in a top view.

公开(公告)号：US20220336318A1

公开(公告)日：2022-10-20

申请号：US17230112

申请日：2021-04-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng LIN ,  Po-Yao LIN ,  Shu-Shen YEH ,  Chin-Hua WANG ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/31

摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, and a first semiconductor die and a second semiconductor die disposed thereon. A ring structure is attached to the package substrate and surrounds the semiconductor dies. A lid structure is attached to the ring structure and disposed over the semiconductor dies, and has an opening exposing the second semiconductor die. A heat sink is disposed over the lid structure and has a portion extending into the opening of the lid structure. A first thermal interface material (TIM) layer is interposed between the lid structure and the first semiconductor die. A second TIM layer is interposed between the extending portion of the heat sink and the second semiconductor die. The first TIM layer has a thermal conductivity higher than the thermal conductivity of the second TIM layer.

公开(公告)号：US20210272869A1

公开(公告)日：2021-09-02

申请号：US17320981

申请日：2021-05-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chin-Hua WANG ,  Po-Yao LIN ,  Feng-Cheng HSU ,  Shin-Puu JENG ,  Wen-Yi LIN ,  Shu-Shen YEH

IPC分类号： H01L23/367 ,  H01L25/065 ,  H01L23/373 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/433

摘要： A method of forming a semiconductor package is provided. The method includes mounting a chip on a package substrate. The method further includes placing a heat spreader over the chip and applying a thermal interface material to a first surface of the heat spreader facing the chip. The heat spreader is flexible. In addition, the method includes attaching the heat spreader to the chip through the thermal interface material by rolling a rod over a second surface of the heat spreader, and the second surface is opposite to the first surface.

公开(公告)号：US20210013160A1

公开(公告)日：2021-01-14

申请号：US17034891

申请日：2020-09-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Chin-Hua WANG ,  Kuang-Chun LEE ,  Po-Yao LIN ,  Shyue-Ter LEU ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/04 ,  H01L23/367 ,  H01L23/10

摘要： Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.