知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

79 records (took 0.014 seconds)

    SEMICONDUCTOR MEMORY DEVICES
    41.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20190164985A1

    公开(公告)日：2019-05-30

    申请号：US16027887

    申请日：2018-07-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiseok LEE ,  Junsoo KIM ,  Hui-Jung KIM ,  Bong-Soo KIM ,  Satoru YAMADA ,  Kyupil LEE ,  Sunghee HAN ,  HyeongSun HONG ,  Yoosang HWANG

    IPC: H01L27/11556 ,  H01L23/532 ,  H01L27/11524 ,  H01L49/02 ,  G11C8/14 ,  G11C7/18

    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

    SEMICONDUCTOR MEMORY DEVICE
    44.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20240422961A1

    公开(公告)日：2024-12-19

    申请号：US18640513

    申请日：2024-04-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

    IPC: H10B12/00

    Abstract: A semiconductor memory device includes a plurality of word lines extending in a first horizontal direction, a plurality of back gate lines extending in the first horizontal direction and alternately arranged with the plurality of word lines in a second horizontal direction different from the first horizontal direction, a plurality of channel layers extending in a vertical direction between a word line and a back gate line adjacent to each other among the plurality of word lines and the plurality of back gate lines, to correspond to columns in the first horizontal direction, a plurality of bit lines extending in the second horizontal direction on the plurality of word lines, the plurality of back gate lines, and the plurality of channel layers and electrically connected to the plurality of channel layers, and a plurality of memory structures electrically connected to the plurality of channel layers.

    SEMICONDUCTOR DEVICE
    45.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240421223A1

    公开(公告)日：2024-12-19

    申请号：US18631839

    申请日：2024-04-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joongchan SHIN ,  Seokhan PARK ,  Kiseok LEE ,  Moonyoung JEONG ,  Jinwoo HAN

    IPC: H01L29/78 ,  H10B12/00

    Abstract: A semiconductor device includes a substrate, a bit line extending in a first direction on the substrate, a first active pattern and a second active pattern on the bit line, a back gate electrode extending in a second direction perpendicular to the first direction across the bit line, and a word line extending in the second direction, wherein the first active pattern and the second active pattern have a minor symmetrical shape with respect to the back gate electrode when viewed in a third direction perpendicular to the first direction and the second direction.

    SEMICONDUCTOR DEVICE
    46.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20240421039A1

    公开(公告)日：2024-12-19

    申请号：US18652381

    申请日：2024-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyungeun CHOI ,  Kiseok LEE

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

    Abstract: A semiconductor device includes a lower chip structure including a memory structure and a lower wiring structure connected to the memory structure and an upper chip structure on the lower chip structure, where the upper chip structure includes an upper base, peripheral transistors below the upper base, an intermediate wiring structure below the upper base and connected to the peripheral transistors, an upper wiring structure on the upper base, a first through-via penetrating the upper base between the upper wiring structure and the intermediate wiring structure, the first through-via connecting the upper wiring structure and the intermediate wiring structure, and a second through-via extending respectively downward and penetrating the upper base between the upper wiring structure and the lower wiring structure, the second through-via connecting the upper wiring structure and the lower wiring structure.

    SEMICONDUCTOR DEVICES HAVING SUPPORTER STRUCTURES
    47.
    发明公开
    SEMICONDUCTOR DEVICES HAVING SUPPORTER STRUCTURES 审中-公开

    公开(公告)号：US20240304691A1

    公开(公告)日：2024-09-12

    申请号：US18668743

    申请日：2024-05-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoin LEE ,  Kiseok LEE

    IPC: H01L29/423 ,  H01L29/40

    CPC classification number: H01L29/423 ,  H01L29/402

    Abstract: A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

    SEMICONDUCTOR DEVICE INCLUDING VERTICAL ACTIVE PILLAR
    48.
    发明公开
    SEMICONDUCTOR DEVICE INCLUDING VERTICAL ACTIVE PILLAR 审中-公开

    公开(公告)号：US20240276712A1

    公开(公告)日：2024-08-15

    申请号：US18435263

    申请日：2024-02-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongjun LEE ,  Keunnam KIM ,  Kiseok LEE

    IPC: H10B12/00 ,  H01L29/78

    CPC classification number: H10B12/482 ,  H01L29/7827

    Abstract: A semiconductor device may include a substrate, a bit line structure, first and second gate electrodes spaced apart from each other, and first and second gate dielectric layers. The substrate may include a first upper active region and a second upper active region spaced apart from each other and protruding upwardly from a lower active region, a first vertical active pillar protruding upwardly from the first upper active region, and a second vertical active pillar protruding upwardly from the second upper active region. The bit line structure may be between the first and second upper active regions. The first and second gate electrodes respectively may surround channel regions of the first and second vertical active pillars. First and second gate dielectric layers respectively may be between the first vertical active pillar and the first gate electrode and between the second vertical active pillar and the second gate electrode.

    SEMICONDUCTOR DEVICE
    49.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240098985A1

    公开(公告)日：2024-03-21

    申请号：US18219229

    申请日：2023-07-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/05 ,  H10B12/315 ,  H10B12/34

    Abstract: A semiconductor device includes a substrate having at least one active region, the at least one active region being defined by an isolation layer, at least one word line extending in a first horizontal direction inside the substrate, the at least one word line crossing the at least one active region, at least one bit line extending in a second horizontal direction orthogonal to the first horizontal direction, the at least one bit line being at a higher vertical level than the at least one word line, and at least one direct contact electrically connecting the at least one bit line to the at least one active region, the at least one direct contact having a maximum width in a third horizontal direction, the third horizontal direction intersecting each of the first horizontal direction and the second horizontal direction at an acute angle.

    SEMICONDUCTOR MEMORY DEVICE
    50.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230354588A1

    公开(公告)日：2023-11-02

    申请号：US18117604

    申请日：2023-03-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kiseok LEE ,  Junhyeok AHN ,  Keunnam KIM ,  Chan-Sic YOON ,  Myeong-Dong LEE

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/02

    Abstract: A semiconductor memory device includes a semiconductor substrate; a device isolation layer defining an active portion in the semiconductor substrate; a bit line structure intersecting the active portion on the semiconductor substrate; a first conductive pad between the bit line structure and the active portion; a bit line contact pattern between the first conductive pad and the bit line structure; a first bit line contact spacer covering a first sidewall of the first conductive pad; and a second bit line contact spacer covering a second sidewall of the first conductive pad, wherein the first conductive pad has a flat bottom surface that is in contact with a top surface of the active portion, and a width of the first bit line contact spacer is different from a width of the second bit line contact spacer.

Patent Agency Ranking