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    Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL)
    42.
    发明授权
    Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL) 有权
    用于模拟锁相环（PLL）的无毛刺带宽切换方案

    公开(公告)号：US09520887B1

    公开(公告)日：2016-12-13

    申请号：US15060198

    申请日：2016-03-03

    Applicant: QUALCOMM Incorporated

    Inventor： Jingcheng Zhuang ,  Jong Min Park ,  Lai Kan Leung ,  Yiwu Tang

    IPC: H03L7/06 ,  H03L7/10 ,  H03L7/089 ,  H03L7/093

    CPC classification number: H03L7/093 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/1075

    Abstract: Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.

    Abstract translation: 本公开的某些方面提供了在锁相环（PLL）中无毛刺带宽切换的技术和装置。 一个示例PLL通常包括包括第一可变电容元件和第二可变电容元件的压控振荡器（VCO），以及包括与电阻器 - 电容器（RC）网络的电阻器并联的第一开关的带宽调整电路。 带宽调整电路被配置为在第一带宽模式下打开第一开关，在从第一带宽模式到第二带宽模式的转变中关闭第一开关，并且基于第一可变电容元件的电压来控制第二可变电容元件的电容 RC网络的一个节点。

    Apparatus and method for generating an oscillating output signal
    44.
    发明授权
    Apparatus and method for generating an oscillating output signal 有权
    用于产生振荡输出信号的装置和方法

    公开(公告)号：US09331704B2

    公开(公告)日：2016-05-03

    申请号：US13757666

    申请日：2013-02-01

    Applicant: QUALCOMM Incorporated

    Inventor： Yiwu Tang ,  Jianyun Hu ,  Chiewcharn Narathong

    IPC: H03L7/00 ,  H03L7/16 ,  H03C3/09 ,  H03B5/12 ,  H03L7/187 ,  H03L7/07 ,  H03L7/10

    CPC classification number: H03L7/16 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1256 ,  H03B5/1296 ,  H03B2201/0208 ,  H03B2201/0216 ,  H03C3/0925 ,  H03C3/0941 ,  H03C3/0958 ,  H03L7/00 ,  H03L7/07 ,  H03L7/101 ,  H03L7/104 ,  H03L7/187

    Abstract: An apparatus for generating an oscillating output signal includes an inductive-capacitive (LC) circuit and a current tuning circuit. The LC circuit includes a primary inductor and a varactor coupled to the primary inductor. A capacitance of the varactor is responsive to a voltage at a control input of the varactor. The current tuning circuit includes a secondary inductor and a current driving circuit coupled to the secondary inductor. The current driving circuit is responsive to a current at a control input of the current driving circuit. An effective inductance of the primary inductor is adjustable via magnetic coupling to the secondary inductor, and a frequency of the oscillating output signal is responsive to the effective inductance of the primary inductor and to the capacitance of the varactor.

    Abstract translation: 用于产生振荡输出信号的装置包括电感 - 电容（LC）电路和电流调谐电路。 LC电路包括耦合到初级电感器的初级电感器和变容二极管。 变容二极管的电容响应于变容二极管的控制输入端的电压。 当前调谐电路包括二次电感器和耦合到次级电感器的电流驱动电路。 电流驱动电路响应于电流驱动电路的控制输入处的电流。 初级电感器的有效电感可通过与次级电感器的磁耦合进行调节，振荡输出信号的频率响应于初级电感器的有效电感和变容二极管的电容。

    Locking multiple voltage-controlled oscillators with a single phase-locked loop
    45.
    发明授权
    Locking multiple voltage-controlled oscillators with a single phase-locked loop 有权
    用单个锁相环锁定多个压控振荡器

    公开(公告)号：US09252790B2

    公开(公告)日：2016-02-02

    申请号：US14251331

    申请日：2014-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Yiwu Tang ,  Jong Min Park ,  Serkan Sayilir ,  Chiewcharn Narathong

    IPC: H03L7/099 ,  H03L7/081

    CPC classification number: H03L7/099 ,  H03L7/081 ,  H03L7/093

    Abstract: Locking multiple VCOs to generate a plurality of LO frequencies, including: receiving a plurality of divided VCO feedback signals from a plurality of VCOs; receiving a reference signal multiplied by a predetermined number of the plurality of VCOs; generating and processing the predetermined number of phase differences between the multiplied reference signal and the plurality of divided VCO feedback signals in a single PLL circuit including a digital loop filter to receive and process the phase differences and generate (produce) a filter output, wherein the digital loop filter includes a plurality of delay cells equal to the predetermined number; and generating and outputting (delayed) control voltages for the plurality of VCOs based on the filter output.

    Abstract translation: 锁定多个VCO以产生多个LO频率，包括：从多个VCO接收多个分割的VCO反馈信号; 接收乘以所述多个VCO的预定数量的参考信号; 在包括数字环路滤波器的单个PLL电路中产生和处理倍增参考信号与多个分压VCO反馈信号之间的预定数量的相位差，以接收和处理相位差并产生（产生）滤波器输出，其中， 数字环路滤波器包括等于预定数量的多个延迟单元; 以及基于滤波器输出产生并输出（延迟的）多个VCO的控制电压。

    Avoiding Spurious Responses with Reconfigurable LO Dividers
    47.
    发明申请
    Avoiding Spurious Responses with Reconfigurable LO Dividers 有权
    用可重配置的分频器避免杂散响应

    公开(公告)号：US20150334711A1

    公开(公告)日：2015-11-19

    申请号：US14644677

    申请日：2015-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Rajagopalan Rangarajan ,  Chiewcharn Narathong ,  Lai Kan Leung ,  Dongling Pan ,  Aleksandar Miodrag Tasic ,  Yiwu Tang

    IPC: H04W72/04 ,  H04W88/06 ,  H04L12/709

    CPC classification number: H04W72/0453 ,  H04B1/005 ,  H04B15/06 ,  H04L45/245 ,  H04W88/06

    Abstract: Methods and apparatus including: setting up a plurality of configurations for a plurality of local oscillator (LO) paths of a carrier aggregation (CA) transceiver operating with a plurality of bands; calculating and comparing frequencies for each LO path of the plurality of LO paths and at least one divider ratio of LO dividers for each band of the plurality of bands to identify frequency conflicts; and reconfiguring the LO dividers for the plurality of LO paths and the plurality of bands when the frequency conflicts are identified.

    Abstract translation: 一种方法和装置，包括：为多个频带操作的载波聚合（CA）收发机的多个本地振荡器（LO）路径建立多个配置; 计算和比较所述多个LO路径中的每个LO路径的频率和所述多个频带中的每个频带的LO分频器的至少一个分频比，以识别频率冲突; 以及当识别出频率冲突时，为多个LO路径和多个频带重新配置LO分频器。

    Programmable frequency divider for local oscillator generation
    49.
    发明授权
    Programmable frequency divider for local oscillator generation 有权
    用于本地振荡器生成的可编程分频器

    公开(公告)号：US09106234B2

    公开(公告)日：2015-08-11

    申请号：US13837463

    申请日：2013-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Yunliang Zhu ,  Yiwu Tang

    IPC: H03B19/14 ,  H03B27/00 ,  H03K3/03 ,  H03L7/18 ,  H03L7/24 ,  H04B1/40 ,  H03L7/00

    CPC classification number: H03L7/00 ,  H03B19/14 ,  H03B27/00 ,  H03K3/0315 ,  H03K3/0322 ,  H03L7/18 ,  H03L7/24 ,  H04B1/40

    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus generates LO signals. The apparatus includes a LO generator module and an injection signal generator module coupled together. The LO generator module has a plurality of LO outputs and a plurality of injection signal inputs. The LO module is configured to generate the LO signals on the LO outputs based on injection signals received on the injection signal inputs. The injection signal generator module has a plurality of LO inputs and a plurality of injection signal outputs. The LO inputs are coupled to the LO outputs. The injection signal outputs are coupled to the injection signal inputs. The injection signal generator module is configured to generate injection signals on the injection signal outputs based on the LO signals received on the LO inputs and based on a received VCO signal.

    Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置产生LO信号。 该装置包括耦合在一起的LO发生器模块和注入信号发生器模块。 LO发生器模块具有多个LO输出和多个注入信号输入。 LO模块被配置为基于在注入信号输入端接收到的注入信号，在LO输出端产生LO信号。 注入信号发生器模块具有多个LO输入和多个注入信号输出。 LO输入耦合到LO输出。 注入信号输出耦合到注入信号输入端。 注入信号发生器模块被配置为基于在LO输入上接收的LO信号并且基于接收的VCO信号，在喷射信号输出上产生喷射信号。

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