公开(公告)号：US20160276009A1

公开(公告)日：2016-09-22

申请号：US14818809

申请日：2015-08-05

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Taehyun Kim ,  Sungryul Kim ,  Seung Hyuk Kang ,  Jung Pill Kim

IPC: G11C11/16 ,  G11C29/44

CPC classification number: G11C11/1675 ,  G11C7/12 ,  G11C11/1659 ,  G11C11/1677 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C29/52

Abstract: Aspects for adjusting resistive memory write driver strength based on write error rate (WER) are disclosed. In one aspect, a write driver strength control circuit is provided to adjust a write current provided to a resistive memory based on a WER of the resistive memory. The write driver strength control circuit includes a tracking circuit configured to determine the WER of the resistive memory based on write operations performed on resistive memory elements. The write driver strength control circuit includes a write current calculator circuit configured to compare the WER to a target WER that represents the desired yield performance level of the resistive memory. A write current adjust circuit in the write driver strength control circuit is configured to adjust the write current based on this comparison. The write driver strength control circuit adjusts the write current to perform write operations while reducing write errors associated with breakdown voltage.

Abstract translation: 公开了基于写入错误率（WER）调整电阻性​​存储器写入驱动器强度的方面。 一方面，提供写入驱动器强度控制电路，以基于电阻性存储器的WER来调整提供给电阻性存储器的写入电流。 写驱动器强度控制电路包括跟踪电路，其被配置为基于对电阻性存储器元件执行的写入操作来确定电阻性存储器的WER。 写驱动器强度控制电路包括写入电流计算器电路，其被配置为将WER与表示电阻性存储器的期望产出性能水平的目标WER进行比较。 写入驱动器强度控制电路中的写入电流调整电路被配置为基于该比较来调整写入电流。 写入驱动器强度控制电路调节写入电流以执行写入操作，同时减少与击穿电压相关联的写入错误。

公开(公告)号：US09379314B2

公开(公告)日：2016-06-28

申请号：US14109234

申请日：2013-12-17

Applicant: QUALCOMM Incorporated

Inventor： Chando Park ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes a free layer. The MTJ also includes a barrier layer coupled to the free layer. The MTJ also has a fixed layer, coupled to the barrier layer. The fixed layer includes a first synthetic antiferromagnetic (SAF) multilayer having a first perpendicular magnetic anisotropy (PMA) and a first damping constant. The fixed layer also includes a second SAF multilayer having a second perpendicular magnetic anisotropy (PMA) and a second damping constant lower than the first damping constant. The first SAF multilayer is closer to the barrier layer than the second SAF multilayer. The fixed layer also includes a SAF coupling layer between the first and the second SAF multilayers.

Abstract translation: 磁隧道结（MTJ）装置包括自由层。 MTJ还包括耦合到自由层的阻挡层。 MTJ还具有耦合到阻挡层的固定层。 固定层包括具有第一垂直磁各向异性（PMA）和第一阻尼常数的第一合成反铁磁（SAF）多层。 固定层还包括具有第二垂直磁各向异性（PMA）和低于第一阻尼常数的第二阻尼常数的第二SAF多层。 第一SAF多层比第二SAF多层更靠近阻挡层。 固定层还包括在第一和第二SAF多层之间的SAF耦合层。

公开(公告)号：US09343135B2

公开(公告)日：2016-05-17

申请号：US14072537

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  G09C1/00 ,  H04L9/08 ,  H04L9/32

CPC classification number: G11C11/1695 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function. The method includes initializing an array of magnetoresistive random-access memory (MRAM) cells to a first logical state, where each of the MRAM cells have a random transition voltage that is greater than a first voltage and less than a second voltage. The transition voltage represents a voltage level that causes the MRAM cells to transition from the first logical state to a second logical state. The method further includes applying a programming signal voltage to each of the MRAM cells of the array to cause at least a portion of the MRAM cells of the array to randomly change state from the first logical state to the second logical state, where the programming signal voltage is greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆功能的方法。 该方法包括将磁阻随机存取存储器（MRAM）单元的阵列初始化为第一逻辑状态，其中每个MRAM单元具有大于第一电压且小于第二电压的随机转变电压。 转换电压表示使MRAM单元从第一逻辑状态转换到第二逻辑状态的电压电平。 该方法还包括将编程信号电压施加到阵列的每个MRAM单元，以使阵列的MRAM单元的至少一部分随机地将状态从第一逻辑状态改变到第二逻辑状态，其中编程信号 电压大于第一电压且小于第二电压。

公开(公告)号：US20160125953A1

公开(公告)日：2016-05-05

申请号：US14994231

申请日：2016-01-13

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Kangho Lee ,  Seung H. Kang ,  Xia Li ,  Wah Nam Hsu

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  G11C17/16 ,  G11C17/165

Abstract: A one time programming (OTP) apparatus unit cell includes magnetic tunnel junctions (MTJs) with reversed connections for placing the MTJ in an anti-parallel resistance state during programming. Increased MTJ resistance in its anti-parallel resistance state causes a higher programming voltage which reduces programming time and programming current.

Abstract translation: 一次性编程（OTP）装置单元包括具有反向连接的磁隧道结（MTJ），用于在编程期间将MTJ置于反并联电阻状态。 在其反并联电阻状态下增加的MTJ电阻会导致更高的编程电压，从而减少编程时间和编程电流。

公开(公告)号：US09142762B1

公开(公告)日：2015-09-22

申请号：US14229427

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Kangho Lee ,  Wei-Chuan Chen ,  Yu Lu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：US20150263266A1

公开(公告)日：2015-09-17

申请号：US14460731

申请日：2014-08-15

Applicant: QUALCOMM Incorporated

Inventor： Matthias Georg Gottwald ,  Chando Park ,  Xiaochun Zhu ,  Kangho Lee ,  Seung Hyuk Kang

IPC: H01L43/08 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673

Abstract: An apparatus includes a perpendicular magnetic anisotropy magnetic tunnel junction (pMTJ) device. The pMTJ device includes a storage layer and a reference layer. The reference layer includes a portion configured to produce a ferrimagnetic effect. The portion includes a first layer, a second layer, and a third layer. The second layer is configured to antiferromagnetically (AF) couple the first layer and the third layer during operation of the pMTJ device.

Abstract translation: 一种装置包括垂直磁各向异性磁隧道结（pMTJ）装置。 pMTJ设备包括存储层和参考层。 参考层包括被配置为产生亚铁磁效应的部分。 该部分包括第一层，第二层和第三层。 第二层被配置为在pMTJ器件的操作期间反铁磁（AF）耦合第一层和第三层。

公开(公告)号：US20150074433A1

公开(公告)日：2015-03-12

申请号：US14072735

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G06F21/70 ,  G06F1/26

CPC classification number: G06F21/70 ,  G06F1/26 ,  G09C1/00 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1695 ,  G11C17/02 ,  G11C17/14 ,  H04L9/0866 ,  H04L9/3278 ,  H04L2209/12

Abstract: One feature pertains to a method of implementing a physically unclonable function that includes providing an array of metal-insulator-metal (MIM) devices, where the MIM devices are configured to represent a first resistance state or a second resistance state and a plurality of the MIM devices are initially at the first resistance state. The MIM devices have a random breakdown voltage that is greater than a first voltage and less than a second voltage, where the breakdown voltage represents a voltage that causes the MIM devices to transition from the first resistance state to the second resistance state. The method further includes applying a signal line voltage to the MIM devices to cause a portion of the MIM devices to randomly breakdown and transition from the first resistance state to the second resistance state, the signal line voltage greater than the first voltage and less than the second voltage.

Abstract translation: 一个特征涉及实现物理上不可克隆的功能的方法，其包括提供金属 - 绝缘体 - 金属（MIM）器件的阵列，其中MIM器件被配置为表示第一电阻状态或第二电阻状态，并且多个 MIM器件最初处于第一电阻状态。 MIM器件具有大于第一电压且小于第二电压的随机击穿电压，其中击穿电压表示使MIM器件从第一电阻状态转变到第二电阻状态的电压。 该方法还包括向MIM器件施加信号线电压以使MIM器件的一部分随机击穿并从第一电阻状态转变到第二电阻状态，信号线电压大于第一电压并小于 第二电压。

公开(公告)号：US08913423B2

公开(公告)日：2014-12-16

申请号：US13772576

申请日：2013-02-21

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Seung H. Kang ,  Xiaochun Zhu

IPC: G11C11/00 ,  G11C15/02 ,  H01L43/02 ,  G06F17/50 ,  G11C11/16

CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

Abstract: An apparatus includes a memory cell including a magnetic tunnel junction (MTJ) structure coupled between a bit line and a source line. The MTJ structure includes a free layer coupled to the bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. A physical dimension of the pinned layer produces an unbalanced offset magnetic field which corresponds to a first switching current of the MTJ structure that enables switching from the first state to the second state when a first voltage is applied to the bit line and corresponds to a second switching current that enables switching from the second state to the first state when the first voltage is applied to the source line.

Abstract translation: 一种装置包括存储单元，其包括耦合在位线和源极线之间的磁性隧道结（MTJ）结构。 MTJ结构包括耦合到位线和固定层的自由层。 自由层的磁矩基本上平行于处于第一状态的被钉扎层的磁矩，并且在第二状态下基本上与销钉层的磁矩反平行。 钉扎层的物理尺寸产生不平衡偏移磁场，其对应于MTJ结构的第一开关电流，当第一电压施加到位线并且对应于第二电压时，能够从第一状态切换到第二状态 当第一电压施加到源极线时，切换电流能够从第二状态切换到第一状态。

公开(公告)号：US20140327508A1

公开(公告)日：2014-11-06

申请号：US13887633

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Daeik D. Kim ,  Kangho Lee ,  David F. Berdy ,  Mario Francisco Velez ,  Jonghae Kim ,  Je-Hsiung Lan ,  Changhan Yun ,  Niranjan Sunil Mudakatte ,  Robert P. Mikulka

IPC: H01F29/14

CPC classification number: H01F21/06 ,  H01F21/08 ,  H01F27/255

Abstract: An inductor tunable by a variable magnetic flux density component is disclosed. A particular device includes an inductor. The device further includes a variable magnetic flux density component (VMFDC) positioned to influence a magnetic field of the inductor when a current is applied to the inductor.

Abstract translation: 公开了一种由可变磁通密度分量调节的电感器。 特定器件包括电感器。 该装置还包括可变磁通密度分量（VMFDC），其定位成当电流施加到电感器时影响电感器的磁场。

公开(公告)号：US20140119097A1

公开(公告)日：2014-05-01

申请号：US14147817

申请日：2014-01-06

Applicant: QUALCOMM Incorporated

Inventor： Wuyang Hao ,  Jungwon Suh ,  Kangho Lee ,  Taehyun Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/72 ,  G11C2213/74

Abstract: A resistance-based memory includes a two-diode access device. In a particular embodiment, a method includes biasing a bit line with a first voltage. The method further includes biasing the sense line with a second voltage. Biasing the bit line and biasing the sense line generates a current through a resistance-based memory element and through one of a first diode and a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.

Abstract translation: 基于电阻的存储器包括二极管接入设备。 在特定实施例中，一种方法包括利用第一电​​压来偏置位线。 该方法还包括利用第二电压来偏置感测线。 偏置位线并偏置感测线通过电阻型存储元件并通过第一二极管和第二二极管之一产生电流。 第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。