公开(公告)号：US11871513B2

公开(公告)日：2024-01-09

申请号：US17564120

申请日：2021-12-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Shigeki Koya ,  Kenji Sasaki

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/24 ,  H01L21/48 ,  H01L23/538 ,  H01L23/467

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H05K1/115 ,  H05K3/245 ,  H01L23/467 ,  H05K2201/09618

Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.

公开(公告)号：US11705509B2

公开(公告)日：2023-07-18

申请号：US16992067

申请日：2020-08-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H03F3/21

CPC classification number: H01L29/7371 ,  H01L21/28575 ,  H01L21/308 ,  H01L21/30612 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/205 ,  H01L29/66318 ,  H01L29/0817 ,  H01L29/0826 ,  H03F3/21

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US11508835B2

公开(公告)日：2022-11-22

申请号：US17569494

申请日：2022-01-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

公开(公告)号：US11508834B2

公开(公告)日：2022-11-22

申请号：US17097937

申请日：2020-11-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Kingo Kurotani ,  Takashi Kitahara ,  Shigeki Koya

IPC: H01L29/73 ,  H01L29/737 ,  H01L23/00 ,  H01L23/482 ,  H01L29/417 ,  H01L29/06 ,  H01L23/535 ,  H01L27/082 ,  H01L29/40 ,  H03F3/19

Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.

公开(公告)号：US11289434B2

公开(公告)日：2022-03-29

申请号：US16904775

申请日：2020-06-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya ,  Yasunari Umemoto ,  Isao Obu ,  Masao Kondo ,  Yuichi Saito ,  Takayuki Tsutsui

IPC: H01L23/66 ,  H01L23/00 ,  H03F3/195

Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.

公开(公告)号：US11251290B2

公开(公告)日：2022-02-15

申请号：US17229564

申请日：2021-04-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.

公开(公告)号：US11240912B2

公开(公告)日：2022-02-01

申请号：US16814902

申请日：2020-03-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao Kondo ,  Shigeki Koya ,  Kenji Sasaki

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/24 ,  H01L21/48 ,  H01L23/538 ,  H01L23/467

Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.

公开(公告)号：US10964693B2

公开(公告)日：2021-03-30

申请号：US16440700

申请日：2019-06-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Shigeki Koya ,  Yasunari Umemoto ,  Takayuki Tsutsui

IPC: H01L27/082 ,  H01L23/00 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H01L29/66 ,  H01L23/498 ,  H01L21/8252 ,  H03F3/20 ,  H03F1/56

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

公开(公告)号：US10541320B2

公开(公告)日：2020-01-21

申请号：US16375724

申请日：2019-04-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Atsushi Kurokawa

IPC: H01L21/00 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L21/306 ,  H01L29/205

Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.

公开(公告)号：US10014832B2

公开(公告)日：2018-07-03

申请号：US15413763

申请日：2017-01-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki Koya

IPC: H03F3/191 ,  H03F1/56 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F1/32 ,  H03F3/217 ,  H03F3/24

CPC classification number: H03F1/565 ,  H03F1/0211 ,  H03F1/3205 ,  H03F3/19 ,  H03F3/21 ,  H03F3/217 ,  H03F3/2176 ,  H03F3/245 ,  H03F2200/381 ,  H03F2200/387 ,  H03F2200/391 ,  H03F2200/451

Abstract: A power amplification module includes: an amplifier that amplifies an input signal and outputs an amplified signal; and a harmonic-termination circuit to which harmonics of the amplified signal are input and the impedance of which is controlled in accordance with the frequency of a harmonic. The power amplification module can operate in a first mode in which a power supply voltage changes in accordance with the average voltage value of the amplified signal over a prescribed time period or in a second mode in which the power supply voltage changes in accordance with the envelope of the input signal. The impedance of the harmonic-termination circuit is controlled such that at least one even-ordered harmonic is short-circuited when the power amplification module operates in the first mode and at least one odd-ordered harmonic of third order or higher is short-circuited when the power amplification module operates in the second mode.