公开(公告)号：US09997361B2

公开(公告)日：2018-06-12

申请号：US15417477

申请日：2017-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Aritra Dasgupta ,  Oleg Gluschenkov ,  Balaji Kannan ,  Unoh Kwon

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/02 ,  H01L21/268 ,  H01L29/51 ,  H01L21/8238

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/02356 ,  H01L21/2636 ,  H01L21/268 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823857 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518

Abstract: Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

公开(公告)号：US09818746B2

公开(公告)日：2017-11-14

申请号：US14994650

申请日：2016-01-13

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Kai Zhao

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823842 ,  H01L29/42372 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517

Abstract: A semiconductor device includes a first transistor formed on a substrate, the first transistor including a channel region positioned on the substrate; a second transistor formed on the substrate, the second transistor including a channel region positioned on the substrate; a high-k dielectric layer disposed on the channel region of the first transistor and the channel region of the second transistor; a first transistor metal gate positioned in contact with the high-k dielectric on the first transistor; a second transistor metal gate positioned in contact with the high-k dielectric on the second transistor; an oxygen absorbing barrier disposed in contact with the high-k dielectric between the first transistor and the second transistor; and a conductive electrode material disposed on the first transistor, the second transistor, and the oxygen absorbing barrier.

公开(公告)号：US09721842B2

公开(公告)日：2017-08-01

申请号：US15058309

申请日：2016-03-02

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/321 ,  H01L21/033 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/66 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/027 ,  H01L21/02 ,  H01L29/51

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

公开(公告)号：US20170207219A1

公开(公告)日：2017-07-20

申请号：US15397042

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L29/417

CPC classification number: H01L27/0924 ,  H01L21/28088 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, depositing a scavenging layer on the first nitride layer, forming a capping layer over the scavenging layer, removing portions of the capping layer and the scavenging layer to expose a portion of the first nitride layer in a n-type field effect transistor (nFET) region of the gate stack, forming a first gate metal layer over the first nitride layer and the capping layer, depositing a second nitride layer on the first gate metal layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US20170207131A1

公开(公告)日：2017-07-20

申请号：US14996572

申请日：2016-01-15

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating a gate stack of a semiconductor device comprises forming a first dielectric layer over a channel region of the device, forming a first nitride layer over the first dielectric layer, forming a first gate metal layer over the first nitride layer, forming a capping layer over the first gate metal layer, removing portions of the capping layer and the first gate metal layer to expose a portion of the first nitride layer in a p-type field effect transistor (pFET) region of the gate stack, depositing a scavenging layer on the first nitride layer and the capping layer, depositing a second nitride layer on the scavenging layer, and depositing a gate electrode material on the second nitride layer.

公开(公告)号：US09515164B2

公开(公告)日：2016-12-06

申请号：US14198976

申请日：2014-03-06

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Balaji Kannan ,  Siddarth Krishnan ,  Unoh Kwon ,  Shahab Siddiqui

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823828 ,  H01L21/225 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28238 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.

Abstract translation: 一种用于形成与N-FET和P-FET栅极共用单个功函数金属的替代金属栅极结构的方法。 该方法分别使用单个光刻步骤来掺杂N-FET和P-FET栅极的高k材料。 掺杂允许使用单个功函金属，其又在金属栅极开口中提供更多的空间，使得块体填充材料可占据更多开口的体积，导致较低电阻门。

公开(公告)号：US09514992B2

公开(公告)日：2016-12-06

申请号：US14706288

申请日：2015-05-07

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Sameer H. Jain ,  Unoh Kwon ,  Zhengwen Li ,  Hari V. Mallela ,  Ayse M. Ozbek ,  Cung D. Tran ,  Reinaldo A. Vega ,  Richard S. Wise

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823468 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823443 ,  H01L27/0886

Abstract: A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include a spacer layer, but the central portion of the trench region is substantially free from the spacer layer. The spacer layer is formed using an angled gas cluster ion beam.

Abstract translation: 半导体器件包括互连级介电层中的沟槽区域。 硅化物层位于沟槽区域的底部。 沟槽区域的相对的短边包括间隔层，但是沟槽区域的中心部分基本上没有间隔层。 使用成角度的气体团簇离子束形成间隔层。

公开(公告)号：US20160329251A1

公开(公告)日：2016-11-10

申请号：US14706288

申请日：2015-05-07

Applicant: International Business Machines Corporation

Inventor： Emre Alptekin ,  Sameer H. Jain ,  Unoh Kwon ,  Zhengwen Li ,  Hari V. Mallela ,  Ayse M. Ozbek ,  Cung D. Tran ,  Reinaldo A. Vega ,  Richard S. Wise

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823468 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823443 ,  H01L27/0886

Abstract: A semiconductor device includes a trench region in an interconnect level dielectric layer. A silicide layer is on the bottom of the trench region. Opposing minor sides of the trench region include a spacer layer, but the central portion of the trench region is substantially free from the spacer layer. The spacer layer is formed using an angled gas cluster ion beam.

Abstract translation: 半导体器件包括互连级介电层中的沟槽区域。 硅化物层位于沟槽区域的底部。 沟槽区域的相对的短边包括间隔层，但是沟槽区域的中心部分基本上没有间隔层。 使用成角度的气体团簇离子束形成间隔层。

公开(公告)号：US09472419B2

公开(公告)日：2016-10-18

申请号：US14919796

申请日：2015-10-22

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Hemanth Jagannathan ,  Balaji Kannan ,  Siddarth A. Krishnan ,  Unoh Kwon ,  Rekha Rajaram

IPC: H01L21/76 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/321 ,  H01L21/033 ,  H01L21/225 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L21/823462 ,  H01L21/02321 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/225 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28229 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3115 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.

Abstract translation: 使用替代金属栅极工艺制造先进节点场效应晶体管的方法。 该方法通过使用由多层薄膜堆叠构成的层，或者在其它实施方案中通过单个阻挡层直接或间接地包括掺杂剂高k电介质。 通过利用多层堆叠的意想不到的蚀刻选择性或单层堆叠的受控蚀刻工艺，可以避免对高k的蚀刻损伤，并且可以严格控制功函数金属厚度，这又可以实现场效应晶体管 具有低Tinv（栅极电容的倒数）不匹配。

公开(公告)号：US20160163603A1

公开(公告)日：2016-06-09

申请号：US14562991

申请日：2014-12-08

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Siddarth Krishnan ,  Unoh Kwon ,  Keith Kwong Hon Wong

IPC: H01L21/8238 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a lower titanium nitride (TiN) first layer and a second layer including one of titanium-aluminum-carbide (TiAlC) and tantalum-aluminum-carbide (TaAlC) formed on the lower TiN first layer.

Abstract translation: 形成晶体管器件的方法包括在衬底上形成界面层和电介质层; 在所述电介质层上形成p型场效应晶体管（PFET）功函数金属层，所述功函数金属层包括下氮化钛（TiN）第一层和包含钛 - 碳化铝（TiAlC）和 形成在下部TiN第一层上的钽 - 碳化铝（TaAlC）。