公开(公告)号：US20230418929A1

公开(公告)日：2023-12-28

申请号：US18343145

申请日：2023-06-28

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard J. Semeria

IPC: G06F21/52

CPC classification number: G06F21/52 ,  G06F2221/034

Abstract: A permissions model for a processor in which permissions are based on the instruction group of an instruction. These permissions may be stored in permissions tables and indexed using the program counter of the instruction. The permissions may identify which of a plurality of instruction groups of an instruction set architecture (ISA) of a processor are permitted to execute from that program counter value. Accordingly, the instruction group of the instruction can be compared to the permitted instruction groups to determine if the instruction has execution permission. In some cases, the instruction-group-based permissions are secondary execution privileges; additional primary execution permissions that are determined using the program counter may also be used.

公开(公告)号：US11803471B2

公开(公告)日：2023-10-31

申请号：US17821312

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： Per H. Hammarlund ,  Lior Zimet ,  Sergio Kolor ,  Sagi Lahav ,  James Vash ,  Gaurav Garg ,  Tal Kuzi ,  Jeffry E. Gonion ,  Charles E. Tucker ,  Lital Levy-Rubin ,  Dany Davidov ,  Steven Fishwick ,  Nir Leshem ,  Mark Pilip ,  Gerard R. Williams, III ,  Harshavardhan Kaushikkar ,  Srinivasa Rangan Sridharan

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F13/28 ,  G06F13/16 ,  G06F13/40 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/109 ,  G06F12/128 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/28 ,  G06F13/4068 ,  G06F15/17368 ,  G06F15/7807 ,  G06F2212/305 ,  G06F2212/657

Abstract: An integrated circuit (IC) including a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers is configured to support scaling of the system using a unified memory architecture. For example, the IC may include an interconnect fabric configured to provide communication between the one or more memory controller circuits and the processor cores, graphics processing units, and peripheral devices; and an off-chip interconnect coupled to the interconnect fabric and configured to couple the interconnect fabric to a corresponding interconnect fabric on another instance of the integrated circuit, wherein the interconnect fabric and the off-chip interconnect provide an interface that transparently connects the one or more memory controller circuits, the processor cores, graphics processing units, and peripheral devices in either a single instance of the integrated circuit or two or more instances of the integrated circuit.

公开(公告)号：US11567861B2

公开(公告)日：2023-01-31

申请号：US17519284

申请日：2021-11-04

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Jeffry E. Gonion ,  Per H. Hammarlund ,  Eran Tamari ,  Lior Zimet ,  Gerard R. Williams, III

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/0871 ,  G06F12/1045

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US11449343B2

公开(公告)日：2022-09-20

申请号：US16220488

申请日：2018-12-14

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Ian D. Kountanis ,  Conrado Blasco ,  Steven Andrew Myers ,  Yannick L. Sierra

IPC: G06F9/38 ,  G06F21/60 ,  G06F9/455 ,  G06F9/30

Abstract: A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

公开(公告)号：US11321095B2

公开(公告)日：2022-05-03

申请号：US16663621

申请日：2019-10-25

Applicant: Apple Inc.

Inventor： Steven A. Myers ,  Jeffry E. Gonion ,  Yannick L. Sierra ,  Thomas Icart

IPC: G06F9/32 ,  G06F9/34 ,  G06F21/52 ,  G06F21/60 ,  G06F9/38 ,  G06F9/455 ,  G06F9/30 ,  G06F21/62

Abstract: Techniques are disclosed relating to protecting branch prediction information. In various embodiments, an integrated circuit includes branch prediction logic having a table that maintains a plurality of entries storing encrypted target address information for branch instructions. The branch prediction logic is configured to receive machine context information for a branch instruction having a target address being predicted by the branch prediction logic, the machine context information including a program counter associated with the branch instruction. The branch prediction logic is configured to use the machine context information to decrypt encrypted target address information stored in one of the plurality of entries identified based on the program counter. In some embodiments, the branch prediction logic decrypts the encrypted target address information by performing a cipher to encrypt the machine context information and performing a Boolean exclusive-OR operation of the encrypted machine context information and the encrypted target address information.

公开(公告)号：US11221962B2

公开(公告)日：2022-01-11

申请号：US16874997

申请日：2020-05-15

Applicant: Apple Inc.

Inventor： Jeffry E. Gonion ,  Bernard Joseph Semeria ,  Michael J. Swift ,  Pradeep Kanapathipillai ,  David J. Williamson

IPC: G06F12/1009 ,  G06F12/14 ,  G06F12/0873 ,  G06F12/1072

Abstract: A system and method for efficiently transferring address mappings and data access permissions corresponding to the address mappings. A computing system includes at least one processor and memory for storing a page table. In response to receiving a memory access operation comprising a first address, the address translation unit is configured to identify a data access permission based on a permission index corresponding to the first address, and access data stored in a memory location of the memory identified by a second address in a manner defined by the retrieved data access permission. The address translation unit is configured to access a table to identify the data access permission, and is configured to determine the permission index and the second address based on the first address. A single permission index may correspond to different permissions for different entities within the system.

公开(公告)号：US20200272464A1

公开(公告)日：2020-08-27

申请号：US16818200

申请日：2020-03-13

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US10754649B2

公开(公告)日：2020-08-25

申请号：US16043772

申请日：2018-07-24

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Jeffry E. Gonion ,  Ali Sazegari ,  Gerard R. Williams, III

IPC: G06F9/30 ,  G06F17/16

Abstract: In an embodiment, a computation engine is configured to perform vector multiplications, producing either vector results or outer product (matrix) results. The instructions provided to the computation engine specify a matrix mode or a vector mode for the instructions. The computation engine performs the specified operation. The computation engine may perform numerous computations in parallel, in an embodiment. In an embodiment, the instructions may also specify an offset with the input memories, providing additional flexibility in the location of operands. More particularly, the computation engine may be configured to perform numerous multiplication operations in parallel and to accumulate results in a result memory, performing multiply-accumulate operations for each matrix/vector element in the targeted locations of the output memory.

公开(公告)号：US20190310854A1

公开(公告)日：2019-10-10

申请号：US15946719

申请日：2018-04-05

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Jeffry E. Gonion ,  Ali Sazegari ,  Erik K. Norden

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a computation engine may perform computations on input vectors having vector elements of a first precision and data type. The computation engine may convert the vector elements from the first precision to a second precision and may also interleave the vector elements as specified by an instruction issued by the processor to the computation engine. The interleave may be based on a ratio of a result precision and the second precision. An extract instruction may be supported to extract results from the computations and convert and deinterleave the vector elements to to provide a compact result in a desired order.

公开(公告)号：US20190034333A1

公开(公告)日：2019-01-31

申请号：US15663115

申请日：2017-07-28

Applicant: Apple Inc.

Inventor： Ali Sazegari ,  Charles E. Tucker ,  Jeffry E. Gonion ,  Gerard R. Williams, III ,  Chris Cheng-Chieh Lee

IPC: G06F12/08 ,  H03M7/30

CPC classification number: G06F12/08 ,  G06F12/00 ,  G06F12/0886 ,  G06F13/00 ,  G06F2212/1016 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3088

Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing are described. In various embodiments, a compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.