公开(公告)号：US11740932B2

公开(公告)日：2023-08-29

申请号：US15971276

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Erik K. Norden

IPC: G06F3/00 ,  G06F9/48 ,  G06N3/063 ,  G06F9/54 ,  G06F13/28 ,  G06F13/16 ,  G06N3/045

CPC classification number: G06F9/4843 ,  G06F9/544 ,  G06F13/1673 ,  G06F13/28 ,  G06N3/045 ,  G06N3/063

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. A neural task manager circuit within the neural processor circuit can switch between tasks in different task queues. Each task queue is configured to store a reference to a task list of tasks for instantiating a neural network. Each task queue can also be assigned a priority parameter. While the neural processor circuit is executing tasks of a first task list and prior to completion of each task, the neural task manager circuit can switch between task queues according to the priority parameters for execution of tasks of a second task list by the neural processor circuit. The neural processor circuit includes one or more neural engine circuits that are configured to perform neural operations by executing the tasks assigned by the task manager.

公开(公告)号：US11537838B2

公开(公告)日：2022-12-27

申请号：US15971882

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20190340486A1

公开(公告)日：2019-11-07

申请号：US15971444

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Christopher L. Mills ,  Erik K. Norden ,  Sung Hee Park

IPC: G06N3/02 ,  G06F7/523 ,  G06F7/50

Abstract: Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.

公开(公告)号：US20190310854A1

公开(公告)日：2019-10-10

申请号：US15946719

申请日：2018-04-05

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Jeffry E. Gonion ,  Ali Sazegari ,  Erik K. Norden

IPC: G06F9/38 ,  G06F9/30

Abstract: In an embodiment, a computation engine may perform computations on input vectors having vector elements of a first precision and data type. The computation engine may convert the vector elements from the first precision to a second precision and may also interleave the vector elements as specified by an instruction issued by the processor to the computation engine. The interleave may be based on a ratio of a result precision and the second precision. An extract instruction may be supported to extract results from the computations and convert and deinterleave the vector elements to to provide a compact result in a desired order.

公开(公告)号：US20240069957A1

公开(公告)日：2024-02-29

申请号：US18361616

申请日：2023-07-28

Applicant: Apple Inc.

Inventor： Liran FISHEL ,  Erik K. Norden

IPC: G06F9/48 ,  G06F9/54 ,  G06F13/16 ,  G06F13/28 ,  G06N3/045 ,  G06N3/063

CPC classification number: G06F9/4843 ,  G06F9/544 ,  G06F13/1673 ,  G06F13/28 ,  G06N3/045 ,  G06N3/063

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. A neural task manager circuit within the neural processor circuit can switch between tasks in different task queues. Each task queue is configured to store a reference to a task list of tasks for instantiating a neural network. Each task queue can also be assigned a priority parameter. While the neural processor circuit is executing tasks of a first task list and prior to completion of each task, the neural task manager circuit can switch between task queues according to the priority parameters for execution of tasks of a second task list by the neural processor circuit. The neural processor circuit includes one or more neural engine circuits that are configured to perform neural operations by executing the tasks assigned by the task manager.

公开(公告)号：US20190340491A1

公开(公告)日：2019-11-07

申请号：US15971882

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Erik K. Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06N3/08 ,  G06F1/32

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20190340490A1

公开(公告)日：2019-11-07

申请号：US15971872

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Erik K. Norden

IPC: G06N3/04 ,  G06F9/50 ,  G06N3/08

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. The neural processor circuit includes neural engine circuits and a neural task manager circuit. The neural task manager circuit includes multiple task queues and a task arbiter circuit. Each task queue stores a reference to a task list of tasks for a machine learning operation. Each task queue may be associated with a priority parameter. Based on the priority of the task queues, the task arbiter circuit retrieves configuration data for a task from a memory external to the neural processor circuit, and provides the configuration data to components of the neural processor circuit including the neural engine circuits. The configuration data programs the neural processor circuit to execute the task. For example, the configuration data may include input data and kernel data processed by the neural engine circuits to execute the task.

公开(公告)号：US12282838B2

公开(公告)日：2025-04-22

申请号：US15971872

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Liran Fishel ,  Erik K. Norden

IPC: G06N3/04 ,  G06F9/50 ,  G06N3/08

Abstract: Embodiments relate to managing tasks that when executed by a neural processor circuit instantiates a neural network. The neural processor circuit includes neural engine circuits and a neural task manager circuit. The neural task manager circuit includes multiple task queues and a task arbiter circuit. Each task queue stores a reference to a task list of tasks for a machine learning operation. Each task queue may be associated with a priority parameter. Based on the priority of the task queues, the task arbiter circuit retrieves configuration data for a task from a memory external to the neural processor circuit, and provides the configuration data to components of the neural processor circuit including the neural engine circuits. The configuration data programs the neural processor circuit to execute the task. For example, the configuration data may include input data and kernel data processed by the neural engine circuits to execute the task.

公开(公告)号：US11487846B2

公开(公告)日：2022-11-01

申请号：US15971444

申请日：2018-05-04

Applicant: Apple Inc.

Inventor： Christopher L. Mills ,  Erik K. Norden ,  Sung Hee Park

IPC: G06F17/16

Abstract: Embodiments relate to a neural processor circuit including a plurality of neural engine circuits, a data buffer, and a kernel fetcher circuit. At least one of the neural engine circuits is configured to receive matrix elements of a matrix as at least the portion of the input data from the data buffer over multiple processing cycles. The at least one neural engine circuit further receives vector elements of a vector from the kernel fetcher circuit, wherein each of the vector elements is extracted as a corresponding kernel to the at least one neural engine circuit in each of the processing cycles. The at least one neural engine circuit performs multiplication between the matrix and the vector as a convolution operation to produce at least one output channel of the output data.

公开(公告)号：US10970078B2

公开(公告)日：2021-04-06

申请号：US15946719

申请日：2018-04-05

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Jeffry E. Gonion ,  Ali Sazegari ,  Erik K. Norden

IPC: G06F9/30 ,  G06F9/38

Abstract: In an embodiment, a computation engine may perform computations on input vectors having vector elements of a first precision and data type. The computation engine may convert the vector elements from the first precision to a second precision and may also interleave the vector elements as specified by an instruction issued by the processor to the computation engine. The interleave may be based on a ratio of a result precision and the second precision. An extract instruction may be supported to extract results from the computations and convert and deinterleave the vector elements to provide a compact result in a desired order.