公开(公告)号：US11989640B2

公开(公告)日：2024-05-21

申请号：US17991373

申请日：2022-11-21

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20190294441A1

公开(公告)日：2019-09-26

申请号：US16423702

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US20190129719A1

公开(公告)日：2019-05-02

申请号：US15800342

申请日：2017-11-01

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3887 ,  G06F17/16

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US10592239B2

公开(公告)日：2020-03-17

申请号：US16423702

申请日：2019-05-28

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38 ,  G06N3/04 ,  G06N3/063

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US20250165747A1

公开(公告)日：2025-05-22

申请号：US19030867

申请日：2025-01-17

Applicant: APPLE INC.

Inventor： Erik Norden ,  Liran FISHEL ,  Sung Hee PARK ,  Jaewon SHIN ,  Christopher L. MILLS ,  Seungjin LEE ,  Fernando A. MUJICA

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20200272464A1

公开(公告)日：2020-08-27

申请号：US16818200

申请日：2020-03-13

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16 ,  G06N3/04 ,  G06N3/063

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.

公开(公告)号：US20240265233A1

公开(公告)日：2024-08-08

申请号：US18614256

申请日：2024-03-22

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US20230099652A1

公开(公告)日：2023-03-30

申请号：US17991373

申请日：2022-11-21

Applicant: Apple Inc.

Inventor： Erik Norden ,  Liran Fishel ,  Sung Hee Park ,  Jaewon Shin ,  Christopher L. Mills ,  Seungjin Lee ,  Fernando A. Mujica

IPC: G06N3/04 ,  G06F1/3296 ,  G06N3/08

Abstract: Embodiments relate to a neural processor circuit with scalable architecture for instantiating one or more neural networks. The neural processor circuit includes a data buffer coupled to a memory external to the neural processor circuit, and a plurality of neural engine circuits. To execute tasks that instantiate the neural networks, each neural engine circuit generates output data using input data and kernel coefficients. A neural processor circuit may include multiple neural engine circuits that are selectively activated or deactivated according to configuration data of the tasks. Furthermore, an electronic device may include multiple neural processor circuits that are selectively activated or deactivated to execute the tasks.

公开(公告)号：US10346163B2

公开(公告)日：2019-07-09

申请号：US15800342

申请日：2017-11-01

Applicant: Apple Inc.

Inventor： Eric Bainville ,  Tal Uliel ,  Erik Norden ,  Jeffry E. Gonion ,  Ali Sazegari

IPC: G06F9/30 ,  G06F17/16 ,  G06F9/38

Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.