公开(公告)号：US20090085042A1

公开(公告)日：2009-04-02

申请号：US12219837

申请日：2008-07-29

申请人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

发明人： Toshiyuki Mine ,  Mitsuharu Tai ,  Akio Shima

IPC分类号： H01L21/20 ,  H01L29/04

CPC分类号： H01L21/268 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/02686 ,  H01L27/1285 ,  H01L29/78642

摘要： A display device having a thin film semiconductor device including a semiconductor thin film having first and second semiconductor regions formed each into a predetermined shape above an insulative substrate, a conductor fabricated into a predetermined shape to the semiconductor thin film and a dielectric film put between the semiconductor thin film and the conductor, in which the semiconductor thin film is a polycrystal thin film with the crystallization ratio thereof exceeding 90% and the difference of unevenness on the surface of the semiconductor thin film does not exceed 10 nm.

摘要翻译： 一种具有薄膜半导体器件的显示装置，该薄膜半导体器件包括半导体薄膜，该半导体薄膜具有在绝缘性基板的上方形成为规定形状的第一半导体区域和第二半导体区域，对该半导体薄膜形成为规定形状的导体， 半导体薄膜和导体，其中半导体薄膜是结晶比率超过90％的多晶薄膜，并且半导体薄膜的表面上的不均匀度不超过10nm。

公开(公告)号：US07375399B2

公开(公告)日：2008-05-20

申请号：US11156558

申请日：2005-06-21

申请人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

发明人： Tomoyuki Ishii ,  Toshiyuki Mine ,  Toshiaki Sano ,  Norifumi Kameshiro

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L27/105 ,  G11C11/405 ,  G11C2207/104 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116

摘要： The present invention is a semiconductor memory device having a logic block and a memory block on the same chip. In the memory device, unit memory cells each include at least two transistors, one of which is a write transistor for storing an electric charge into and releasing it from an electric charge storage node, and the other is a read transistor whose conductance in a channel region provided between a source and drain of the read transistor is modulated dependently on the amount of electric charge stored into or released from the electric charge storage node by the write transistor. The read transistor has a gate-insulating film thicker than that of a transistor provided in the logic block, and uses the same diffusion layer structure as that of the logic block.

摘要翻译： 本发明是具有在同一芯片上的逻辑块和存储器块的半导体存储器件。 在存储器件中，单元存储单元每个都包括至少两个晶体管，其中之一是用于存储电荷并将其从电荷存储节点释放的写入晶体管，另一个是在沟道中的电导 读取晶体管的源极和漏极之间的区域被调制，取决于由写入晶体管存储或从电荷存储节点释放的电荷的量。 读取晶体管具有比设置在逻辑块中的晶体管更厚的栅极绝缘膜，并且使用与逻辑块相同的扩散层结构。

公开(公告)号：US20080073705A1

公开(公告)日：2008-03-27

申请号：US11829248

申请日：2007-07-27

申请人： Digh HISAMOTO ,  Itaru Yanagi ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yutaka Okuyama

发明人： Digh HISAMOTO ,  Itaru Yanagi ,  Yasuhiro Shimamoto ,  Toshiyuki Mine ,  Yutaka Okuyama

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0425 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833

摘要： A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.

摘要翻译： 作为具有绝缘体栅极场效应晶体管的结构的非易失性存储单元的电荷捕获层的栅极介质通过层叠由氧化硅膜形成的第一绝缘体，由氮化硅膜形成的第二绝缘体 由半导体衬底的主表面依次由含有氧的氮化硅膜构成的第三绝缘体和由氧化硅膜形成的第四绝缘体构成。 孔从栅电极侧注入电荷捕获层。 因此，由于可以在没有孔穿过与沟道和第一绝缘体接触的界面的情况下实现操作，所以不会发生由于第一绝缘体的劣化导致的重写耐久性和电荷捕获特性的劣化， 并且可以实现高效的重写（写入和擦除）特性和稳定的电荷捕获特性。

公开(公告)号：US20070134835A1

公开(公告)日：2007-06-14

申请号：US11566952

申请日：2006-12-05

申请人： Hiroshi Fukuda ,  Toshiyuki Mine

发明人： Hiroshi Fukuda ,  Toshiyuki Mine

IPC分类号： H01L21/00 ,  H01L29/84

CPC分类号： H01H59/0009 ,  G02B6/357 ,  G02B6/358 ,  G02B6/3584 ,  H01H2001/0042 ,  H01H2001/0063

摘要： A MEMS switch is provided with a substrate, a diaphragm which is disposed on the substrate with interposing a cavity therebetween and is elastically deformed by electrostatic force, a switch drive electrode disposed on the substrate, and a switch drive electrode disposed on the diaphragm. Further, a charge accumulation electrode is disposed on the diaphragm between the switch drive electrode and the switch drive electrode. When charge is accumulated in the charge accumulation electrode, electrostatic force is generated between the charge accumulation electrode and the switch drive electrode, thereby deforming the diaphragm. Accordingly, a small-sized bistable MEMS switch whose structure is simple, whose holding state is stable for a long period, and which can be easily mounted together with a semiconductor integrated circuit can be realized.

摘要翻译： MEMS开关设置有基板，隔膜，其设置在基板上，在其间插入空腔并且通过静电力弹性变形，设置在基板上的开关驱动电极和设置在隔膜上的开关驱动电极。 此外，电荷累积电极设置在开关驱动电极和开关驱动电极之间的隔膜上。 当在电荷累积电极中积累电荷时，在电荷累积电极和开关驱动电极之间产生静电力，从而使隔膜变形。 因此，可以实现其结构简单，其保持状态长时间稳定并且可以容易地与半导体集成电路一起安装的小尺寸双稳态MEMS开关。

公开(公告)号：US07195976B2

公开(公告)日：2007-03-27

申请号：US10851350

申请日：2004-05-24

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistor can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US06982468B2

公开(公告)日：2006-01-03

申请号：US10942014

申请日：2004-09-16

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

公开(公告)号：US20050272198A1

公开(公告)日：2005-12-08

申请号：US11144593

申请日：2005-06-06

申请人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

发明人： Hirotaka Hamamura ,  Toshiyuki Mine ,  Natsuki Yokoyama

IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L21/28282 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/792

摘要： Conventionally, a MONOS type nonvolatile memory is fabricated by subjecting a silicon nitride film to ISSG oxidation to form a top silicon oxide film of ONO structure. If the ISSG oxidation conditions are severe, repeats of programming/erase operation cause increase of interface state density (Dit) and electron trap density. This does not provide a sufficient value of the on current, posing a problem in that the deterioration of charge trapping properties cannot be suppressed. For the solution to the problem, the silicon nitride film is oxidized by means of a high concentration ozone gas to form the top silicon oxide film.

摘要翻译： 通常，通过使氮化硅膜进行ISSG氧化来形成ONO结构的顶部氧化硅膜来制造MONOS型非易失性存储器。 如果ISSG氧化条件严重，编程/擦除操作的重复会导致界面态密度（Dit）和电子陷阱密度的增加。 这不能提供足够的导通电流值，这导致不能抑制电荷俘获特性的劣化的问题。 为了解决这个问题，氮化硅膜通过高浓度的臭氧气体被氧化，形成顶部氧化硅膜。

公开(公告)号：US20050090058A1

公开(公告)日：2005-04-28

申请号：US10954102

申请日：2004-09-30

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01M10/0525 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C27/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/283 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/76 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119 ,  H01M2/16

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US06521943B1

公开(公告)日：2003-02-18

申请号：US09520346

申请日：2000-03-07

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

摘要翻译： 公开了一种半导体器件（例如非易失性半导体存储器件）及其形成方法。 该器件包括在栅极绝缘膜上具有非晶硅膜的第一层或多晶硅薄膜或非晶硅和多晶硅的组合的膜的栅电极（例如，浮栅电极）。 当膜包括多晶硅时，膜的厚度小于10nm。 可以在第一层上或覆盖第一层上提供较厚的多晶硅膜。 存储器件可以显着增加写入/擦除电流，而不会在施加应力之后增加低电场漏电流，这反过来大大降低了写入/擦除时间。 在形成半导体器件时，可以在栅极绝缘膜上提供薄的非晶或多晶硅膜，以及设置在非晶硅膜上的薄绝缘膜，其上设置有较厚的多晶硅膜或覆盖薄绝缘膜。 在薄硅膜是非晶硅的情况下，其然后可以多晶化，尽管不需要。 还公开了基于层厚度的非晶硅层的选择性结晶的技术。

公开(公告)号：US06444554B1

公开(公告)日：2002-09-03

申请号：US10011731

申请日：2001-12-11

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiakl Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21283

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。